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[VHDL-FPGA-Verilog] Total: 66970 | <<First  <Previous  Next>  Last>>  Page: 1/2233  

1. qiangda.zip

<1045322408> uploading at 2017-06-01 18:30:54
Describe: Responder, 3 answer, that corresponds to three switches, who first press, LED output display
Plat: VHDL | Size: 1798KB | Downloads:0

2. pwm_generate_module.rar

<542075329> uploading at 2017-06-01 09:20:14
Describe: Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
Plat: VHDL | Size: 1KB | Downloads:0

3. async_fifo.rar

<542075329> uploading at 2017-06-01 09:17:43
Describe: Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)
Plat: VHDL | Size: 1KB | Downloads:0

4. Butterfly_lovers_beef.rar

<542075329> uploading at 2017-06-01 09:14:55
Describe: Verilog prepared buzzer music Butterfly Lovers . The system clock is 50MHz.
Plat: VHDL | Size: 1KB | Downloads:0

5. VGA.rar

<542075329> uploading at 2017-06-01 09:09:36
Describe: Vga with verilog display colorbar image. Includes VGA driver with a resolution of 640* 480.
Plat: VHDL | Size: 1KB | Downloads:0

6. LCD12864.rar

<542075329> uploading at 2017-06-01 09:04:49
Describe: Lcd12864 Chinese display. You can change the code by querying ASCII.
Plat: VHDL | Size: 1KB | Downloads:0

7. syncfifo.rar

<542075329> uploading at 2017-06-01 08:59:47
Describe: A simple single port ram based on the synchronization fifo. Can only support write-only or read-only.
Plat: VHDL | Size: 1KB | Downloads:0

8. SerialComunications.rar

<diegobanol.udea> uploading at 2017-06-01 07:17:43
Describe: Decoder and encoder for the serial communication
Plat: VHDL | Size: 197KB | Downloads:0

9. RapidIO_avalonst.rar

<zmm700> uploading at 2017-05-31 22:50:11
Describe: rapidio altera
Plat: PDF | Size: 244KB | Downloads:0

10. seqdet.rar

<2223178014> uploading at 2017-05-31 20:17:21
Describe: 10010 sequence detector based on Verilog hdl.
Plat: VHDL | Size: 266KB | Downloads:0

11. song.rar

<2223178014> uploading at 2017-05-31 18:57:31
Describe: Using Hardware Description Language Verilog HDL written with peripheral buzzer to achieve fixed music.
Plat: VHDL | Size: 2KB | Downloads:0

12. scan_led.rar

<2223178014> uploading at 2017-05-31 18:55:34
Describe: Using Hardware Description Language Verilog HDL written to achieve dynamic scanning display code.
Plat: VHDL | Size: 1KB | Downloads:0

13. s2p.rar

<2223178014> uploading at 2017-05-31 18:53:37
Describe: convert serial to parallel
Plat: VHDL | Size: 1KB | Downloads:0

14. LEDWATER.rar

<2223178014> uploading at 2017-05-31 18:50:23
Describe: led water
Plat: VHDL | Size: 1KB | Downloads:0

15. led_display.rar

<2223178014> uploading at 2017-05-31 17:48:27
Describe: led display
Plat: VHDL | Size: 1KB | Downloads:0

16. FPGA-DSP.zip

<zhuheting1515> uploading at 2017-05-31 10:36:17
Describe: FPGA digital signal processing principle and method routines
Plat: VHDL | Size: 4795KB | Downloads:0

17. led_flsah.zip

<zhuheting1515> uploading at 2017-05-31 10:33:14
Describe: The VHDL language implements the digital tube dynamic display
Plat: VHDL | Size: 447KB | Downloads:0

18. traffic_control.zip

<zhuheting1515> uploading at 2017-05-31 10:30:25
Describe: The state machine implements traffic light control
Plat: VHDL | Size: 256KB | Downloads:1

19. EEPROM.zip

<zhuheting1515> uploading at 2017-05-31 10:14:13
Describe: The verilog language implements read and write to the EEPROM
Plat: Others | Size: 4080KB | Downloads:0

20. read_test.zip

<2939969915> uploading at 2017-05-30 22:44:00
Describe: Used to test altera internal ROM memory, write a predetermined value to the inside, and then read out, through signaltap ii observation, online simulation
Plat: Others | Size: 3358KB | Downloads:0

21. vevxj.zip

<jiangyun1951zheng> uploading at 2017-05-29 13:17:35
Describe: esprit algorithm signal frequency interference can be assessed A window function design FIR digital band-pass filter, There ULA CRB curve.
Plat: Objective-C | Size: 6KB | Downloads:0

22. jsq.rar

<865154659> uploading at 2017-05-29 12:45:48
Describe: This is a hexadecimal counter. When the reset signal is valid, the value is 0 and the carry is 0. When the reset signal is 0 and the clock signal is rising edge, the counter starts counting. When the value is 59, the carry is 1, Then the value is zeroed
Plat: VHDL | Size: 5KB | Downloads:0

23. GPIO_PL_IPCORE.zip

<lisq789> uploading at 2017-05-28 19:32:59
Describe: VIVADO 2016.4 u901A u8FC7PS u548CP u5B4E u73B0GPIO u63A5 u53E3 u7684 u5B9E u73B0 u65B9 u5F0F uFF083 uFF09 uFF0C u8FD9 u662F u5B8C u6574 u5DE5 u7A0B uFF01
Plat: Visual C++ | Size: 23336KB | Downloads:0

24. GPIO_PS_EMIO.zip

<lisq789> uploading at 2017-05-28 19:25:33
Describe: VIVADO 2016.4 u901A u8FC7PS u548CPL u5B9E u73B0GPIO u63A5 u53E3 u7684 u5B9E u73B0 u65B9 u5F0F uFF082 uFF09 uFF0C u8FD9 u662F u5B8C u6574 u5DE5 u7A0B.
Plat: Visual C++ | Size: 7083KB | Downloads:0

25. GPIO_PS_MIO.zip

<lisq789> uploading at 2017-05-28 19:20:27
Describe: VIVADO 2016.4 u901A u8FC7PS u548CPL u5B9E u73B0GPIO u63A5 u53E3 u7684 u5B9E u73B0 u65B9 u5F0F uFF081 uFF09 uFF0C u8FD9 u662F u5B8C u6574 u5DE5 u7A0B uFF01
Plat: Visual C++ | Size: 7528KB | Downloads:0

26. dzz.rar

<1099919853> uploading at 2017-05-28 17:08:59
Describe: VHDL language FPGA electronic clock, to achieve basic electronic clock function
Plat: VHDL | Size: 3545KB | Downloads:0

27. blink_led_3freq.rar

<achikwema> uploading at 2017-05-28 15:32:50
Describe: blink led with 3 frequencies on de2-115 board
Plat: VHDL | Size: 354KB | Downloads:0

28. uart2bus_testbench_latest.tar.gz

<3205080221> uploading at 2017-05-28 11:40:29
Describe: Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a preliminary understanding and master.
Plat: VHDL | Size: 988KB | Downloads:0

29. spi_latest.tar.gz

<3205080221> uploading at 2017-05-28 11:36:24
Describe: Spi controller verilog development program, very suitable for verilog development designers to learn, but also interested in spi developers to provide a simple understanding
Plat: VHDL | Size: 547KB | Downloads:0

30. verilog-SDRAM.rar

<1203318150> uploading at 2017-05-28 11:24:22
Describe: Written in verilog language SDRAM read and write controller procedures, the test is valid.
Plat: VHDL | Size: 20719KB | Downloads:0
[VHDL-FPGA-Verilog] Total 66970 | <<First  <Previous  Next>  Last>>  Page: 1/2233