1. CLK_DIV.zip

<fightsea> uploading at 2012-02-24 00:58:15
Describe: verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the target clock. Have been actual tested
Plat: VHDL | Size: 1KB | Downloads:0

2. UARTNUMBER.rar

<wymwymwym> uploading at 2012-02-23 22:12:46
Describe: Through the communication control digital tube display. With the successful application to the project. Through the S7200 free protocol to send data to be displayed to the MCU to control the 4 digital tube display.
Plat: C++ Builder | Size: 54KB | Downloads:0

3. writ.rar

<253464483> uploading at 2012-02-23 22:09:42
Describe: Inside the GUSS read module, has very high use value, is the main parameters and output read update
Plat: VHDL | Size: 1KB | Downloads:0

4. rite.rar

<253464483> uploading at 2012-02-23 22:06:25
Describe: The procedures of the the GUSS algorithm inside of the read module, very valuable, the use of appropriate development group can be modified into other module functions.
Plat: VHDL | Size: 1KB | Downloads:0

5. GM00.rar

<253464483> uploading at 2012-02-23 22:04:24
Describe: Gaussian algorithm for top-level file contains a lot of modules, as well as noise cancellation, the process of the algorithm clearly listed..
Plat: VHDL | Size: 10KB | Downloads:0

6. pixel_mat.rar

<253464483> uploading at 2012-02-23 22:02:28
Describe: Pixels updated documentation for the occasion of the Gaussian application is very stable and very good design clock..
Plat: VHDL | Size: 342KB | Downloads:0

7. gau66.rar

<253464483> uploading at 2012-02-23 21:58:34
Describe: Gaussian algorithm documentation, very detailed design process, really good, oh, there are opportunities for cooperation.
Plat: VHDL | Size: 1537KB | Downloads:0

8. clock-design-verilog-Fpga.rar

<kaiakino.2> uploading at 2012-02-23 21:12:59
Describe: using verilog design watch, digital circuit design, FPGA
Plat: VHDL | Size: 1490KB | Downloads:0

9. crc.rar

<981007570> uploading at 2012-02-23 19:55:59
Describe: The agreement with EPC C1G2 digital baseband crc verify module source code
Plat: Windows_Unix | Size: 2KB | Downloads:0

10. clk_gen.rar

<981007570> uploading at 2012-02-23 19:52:33
Describe: The agreement with EPC C1G2 digital baseband global synchronous clock produces module source code
Plat: Windows_Unix | Size: 2KB | Downloads:0

11. pie_encode.rar

<981007570> uploading at 2012-02-23 19:50:33
Describe: The agreement with EPC C1G2 digital baseband PIE coding module source code
Plat: Unix_Linux | Size: 1KB | Downloads:0

12. vhdl.zip

<954989730> uploading at 2012-02-23 19:47:52
Describe: Electronic clock and alarm, vhdl language program structure is compact, very quickly due to the FPGA clock, the clock is very accurate
Plat: VHDL | Size: 179KB | Downloads:0

13. channel_fir.rar

<981007570> uploading at 2012-02-23 19:46:39
Describe: Used for wireless digital baseband channel selection filter, verilog code
Plat: Windows_Unix | Size: 4KB | Downloads:0

14. clock.rar

<75296834> uploading at 2012-02-23 19:44:42
Describe: Implemented digital electronic clock function, including, points, seconds, can show
Plat: VHDL | Size: 1452KB | Downloads:0

15. FPL2010_v20100901_publicado.zip

<512337109> uploading at 2012-02-23 19:18:03
Describe: Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA.
Plat: VHDL | Size: 573KB | Downloads:0

16. Quick51jump.zip

<txtter> uploading at 2012-02-23 16:43:25
Describe: quick51 jump
Plat: C-C++ | Size: 13KB | Downloads:0

17. guangbobaoshi.rar

<380741862> uploading at 2012-02-23 16:41:02
Describe: ) when the timer operation to 59 49 seconds to strike the start point, each named 1 s stop call 1 s, resonance that six ring, before 5 ring for bass, frequency for 740 Hz Finally a ring for high notes, frequency for 1 KHz (2) should have at least provides a display.
Plat: VHDL | Size: 38KB | Downloads:0

18. baoshi.rar

<380741862> uploading at 2012-02-23 16:35:04
Describe: (1) when the timer operation to 59 49 seconds to strike the start point, each named 1 s stop call 1 s, resonance that six ring, before 5 ring for bass, frequency for 740 Hz Finally a ring for high notes, frequency for 1 KHz (2) should have at least provides a display.
Plat: VHDL | Size: 38KB | Downloads:0

19. FPGA_27demos.rar

<yhelp> uploading at 2012-02-23 15:48:03
Describe: Some of the basic instance based on fpga, practicability, module can be used directly
Plat: VHDL | Size: 1249KB | Downloads:0

20. System_Demons.rar

<dandansong123> uploading at 2012-02-23 11:45:39
Describe: 0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Plat: VHDL | Size: 520KB | Downloads:0