Describe: USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)

File list(time 2005102220~2009122017)(Click to check if it's the file you need, and recomment it at the bottom):
  usbf_crc16.v
  usbf_crc5.v
  usbf_defines.v
  usbf_ep_rf.v
  usbf_ep_rf_dummy.v
  usbf_idma.v
  usbf_mem_arb.v
  usbf_pa.v
  usbf_pd.v
  usbf_pe.v
  usbf_pl.v
  usbf_rf.v
  usbf_top.v
  usbf_utmi_if.v
  usbf_utmi_ls.v
  usbf_wb.v

 To Search: opencore usb verilog usb ip core usb core USB2.0 verilog USB2.0 usb2.0 in verilog 

 [OpenCORE_brochure.rar] - OpenCORE provides essential mediafeatures for device development for android
 [Kalman_matlab00000.rar] - user interface with Matlab Kalman filtering procedures, Matlab-Tracking- GUI, Notes, for all three sample study, can understand the design of the Kalm
 [ethernet_verilog.rar] - This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.

 [usb1.1IP-CORE-VHDL.zip] - Sample program for usb1.1 IP core design, VHDL source code
 [usb2.0IPCore.rar] - usb20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
 [usb2.0IP_core_Verilog.rar] - complete with verilog language development usb2.0 IP source code, including documentation, Simulation documents
 [usb20.rar] - Common interface usb2.0 development of the verilog code
 [fat16_SouceCode .rar] - the source code for fat16, including fat16.c and filesys.c. welcome for your referece.
 [usb_HOST.rar] - Outstanding Master s Thesis, embedded usb host design, on the USB protocol specification, MASS STORAGE agreement in detail.