Describe: ethernet MAC controller VHDL realize

File list(Click to check if it's the file you need, and recomment it at the bottom):
  ethernet
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  ........\.....\.......\eth_host.v
  ........\.....\.......\eth_memory.v
  ........\.....\.......\eth_phy.v
  ........\.....\.......\eth_phy_defines.v
  ........\.....\.......\tb_cop.v
  ........\.....\.......\tb_ethernet.v
  ........\.....\.......\tb_ethernet_with_cop.v
  ........\.....\.......\tb_eth_defines.v
  ........\.....\.......\tb_eth_top.v
  ........\.....\.......\wb_bus_mon.v
  ........\.....\.......\wb_master32.v
  ........\.....\.......\wb_master_behavioral.v
  ........\.....\.......\wb_model_defines.v
  ........\.....\.......\wb_slave_behavioral.v
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  ........\doc
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  ........\...\ethernet_datasheet_OC_head.pdf
  ........\...\ethernet_product_brief_OC_head.pdf
  ........\...\eth_design_document.pdf
  ........\...\eth_speci.pdf
  ........\...\src
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  ........\...\...\ethernet_datasheet_OC_head.doc
  ........\...\...\ethernet_product_brief_OC_head.doc
  ........\...\...\eth_design_document.doc
  ........\...\...\eth_speci.doc
  ........\README.txt
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  ........\...\.......\eth_clockgen.v
  ........\...\.......\eth_cop.v
  ........\...\.......\eth_crc.v
  ........\...\.......\eth_defines.v
  ........\...\.......\eth_fifo.v
  ........\...\.......\eth_maccontrol.v
  ........\...\.......\eth_macstatus.v
  ........\...\.......\eth_miim.v
  ........\...\.......\eth_outputcontrol.v
  ........\...\.......\eth_random.v
  ........\...\.......\eth_receivecontrol.v
  ........\...\.......\eth_register.v
  ........\...\.......\eth_registers.v
  ........\...\.......\eth_rxaddrcheck.v
  ........\...\.......\eth_rxcounters.v
  ........\...\.......\eth_rxethmac.v
  ........\...\.......\eth_rxstatem.v
  ........\...\.......\eth_shiftreg.v
  ........\...\.......\eth_spram_256x32.v
  ........\...\.......\eth_top.v
  ........\...\.......\eth_transmitcontrol.v
  ........\...\.......\eth_txcounters.v
  ........\...\.......\eth_txethmac.v
  ........\...\.......\eth_txstatem.v
  ........\...\.......\eth_wishbone.v
  ........\...\.......\timescale.v
  ........\...\.......\TODO
  ........\...\.......\xilinx_dist_ram_16x32.v
  ........\sim
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  ........\...\rtl_sim
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  ........\...\.......\...\cds.lib
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 To Search: Ethernet ethernet VHDL  ethernet mac vhdl VHDL ethernet rxethm VHDL ETHERNE VHDL MAC 

 [DM9000EP_Product_v1.0.rar] - DM9000 technical documents ISA to Ethernet MAC Controller with Intergrated 10/100 PHY
 [NAND_Controller_and_ECC_VHDL.zip] - NAND read and write complete control of the VHDL program modules, including the seamless connection of ecc checking procedures, very worthwhile to lea
 [RGBtoYCbCr.zip] - FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.

 [CCIR601.rar] - BT601 specification
 [Huaweitechnical1.rar] - Huawei's internal learning, very good agreement on the basis of network knowledge
 [xilinx0424.rar] - Xilinx Chinese official training materials (all), Xilinx novice users required materials.
 [IEEE8021xbasedEthernetMAC.rar] - This is a master's degree thesis, whose name is based on the IEEE8021 Ethernet Access Control Chip Design
 [huffman.rar] - test my account and my password
 [mii.rar] - MII Ethernet PHY port physical layer transceiver procedures, can be used as the development of reference
 [ethtoe1.rar] - master paper the design and implentation of Ethernet+over+E1