Description: Serial debugging assistant sends the number of hexadecimal 1-16 to the FPGA, which is shown by the lamp. The baud rate can be set.

Plat: Verilog | Size: 441KB | Downloads: 1

Description: Program for sending data from computer and receiving data by FPGA, UART module

Plat: Verilog | Size: 17969KB | Downloads: 1

Description: SPI program has been applied and verified in practice

Plat: Verilog | Size: 4KB | Downloads: 3

Description: Design of 16-bit synchronous adder and multiplier
Requirements: (1) Analysis of 16-bit synchronous adder and multiplier structure and circuit characteristics;
(2) Design with hardware description language;
(3) Writing test simulation and simulation.
Design a simple frequency meter with 8 digit display. Requirement:
It can test 10 Hz ~ 10 MHz square wave signal.
(2) The reference clock input by the circuit is 1Hz, which requires the measured value to be output in the form of 8421BCD code.
(3) The system has reset keys;
(4) The design is based on Verilog HDL with the method of hierarchical module.

Plat: Verilog | Size: 20KB | Downloads: 1

Description: rgb to YCbCr converter

Plat: Vivado | Size: 4719KB | Downloads: 0

Description: Multipelexer Verilog code

Plat: Verilog | Size: 2KB | Downloads: 0

Description: Solutions for computer experiment.

Plat: Others | Size: 33992KB | Downloads: 1

Description: Computer composition and system design

Plat: Others | Size: 12633KB | Downloads: 1

Description: Verilog instruction book

Plat: Others | Size: 6931KB | Downloads: 1

Description: Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code

Plat: Verilog | Size: 7KB | Downloads: 6

Description: Various functions of Verilog are realized, and the clock frequency is easy to adjust.

Plat: Verilog | Size: 355KB | Downloads: 0

Description: The system Verilog verification platform of the Peace Dispute Machine module, including the modelsim/questasim project file, is compiled and can be used directly.

Plat: Verilog | Size: 248KB | Downloads: 1

Description: FIR, VHDL CODE and simulation data

Plat: VHDL | Size: 27KB | Downloads: 2

Description: All digital phase locked loop project

Plat: VHDL | Size: 30150KB | Downloads: 1

Description: Design a 1MHz FIR low pass filter.
Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence.
The elements of the sequence are the 10 Numbers [0-9], each of which corresponds to a 4-bit binary representation.
Let's say 5 is equal to 0101, and 9 is equal to 1001.
The length of the input data sequence is 256.
First output the encoding of each element, and then output the data sequence corresponding Huffman coding sequence.
Requirements:
(1) clock signal frequency 16MHz;
(2) input signal bit width of 8bits, symbol rate of 16MHz
Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient
(4) write the test simulation program.

Plat: VHDL | Size: 178KB | Downloads: 11

Description: Design a 1MHz FIR low pass filter.
Requirements:
(1) clock signal frequency 16MHz;
(2) input signal bit width of 8bits, symbol rate of 16MHz
Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient
(4) write the test simulation program.

Plat: VHDL | Size: 334KB | Downloads: 7

Description: The barker code correlator can detect the barker code sequence peak, and can detect the barker code sequence peak in the case of 1bits error.
Barker code is a binary code group with special rules proposed by r.h. barker in the early 1950s.
It is an aperiodic sequence, an n-bit barker code (x1, x3...
Xn), each symbol can only value +1 or -1.
And the barker code for eleven is 11 'b11100010010.

Plat: VHDL | Size: 365KB | Downloads: 3

Description: Design a simple frequency meter with 8-digit display.
Requirements:
(1) able to test 10Hz~10MHz square wave signal;
The circuit input reference clock is 1Hz, the measurement value in 8421BCD code output;
The system has reset key;
(4) using the method of hierarchical module, Verilog HDL design.
Write the test simulation program

Plat: VHDL | Size: 2964KB | Downloads: 4

Description: Comprehensive training platform operation instruction and extended module experiment instruction

Plat: Verilog | Size: 4761KB | Downloads: 0

Description: Music Player Based on VHDL/FPGA/verilog

Plat: VHDL | Size: 68KB | Downloads: 0

Description: aopdp opowdo pawopd kpoawd

Plat: digsilent | Size: 6KB | Downloads: 0

Description: Frequency Meter Based on FPGA and Digital Tube Display the Frequency to be Measured

Plat: VHDL | Size: 1349KB | Downloads: 0

Description: The basic gate circuits, and gates, non-gates, exclusive or gates, and non-gates, or gates, and non-gates can be implemented in a case-by-case manner.

Plat: VHDL | Size: 23400KB | Downloads: 0

Description: The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the data range of simulation weight in the operation process is required.

Plat: matlab | Size: 928KB | Downloads: 0

Description: An adaptive uniform linear antenna array based on LMS algorithm is simulated. The antenna array consists of four omnidirectional antennas with adjacent arrays spaced at half of the wavelength.

Plat: matlab | Size: 2551KB | Downloads: 0

Description: Design of low-pass, band-pass and band-stop filters with Hamming window

Plat: matlab | Size: 1KB | Downloads: 1

Description: minxmum system of fpga based on EP2C8Q208

Plat: Verilog | Size: 25554KB | Downloads: 0

Description: Common Verilog code, easy to write program direct call, no need to design from scratch.

Plat: WINDOWS | Size: 3850KB | Downloads: 0

Description: Sequence detection, used to detect sequences, can detect continuous sequences.

Plat: Verilog | Size: 123KB | Downloads: 0

Description: A carry free arithmetic operation can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). In QSD, each digit can be represented by a number from -3 to 3. Carry free addition and other operations on a large number of digits such as 64, 128, or more can be implemented with constant delay and less complexity. Design is simulated & synthesized using Modelsim6.0, Micro wind and Leonardo Spectrum.

Plat: Others | Size: 54KB | Downloads: 0