ligh1 2020-03-01 15:49:44
Description: driver of HDMI using fpga
Plat: Verilog | Size: 3617KB | Downloads: 1
Astra123 2020-03-01 14:45:11
Description: Ram Tester for checking Static RAM ICs
Plat: LINUX | Size: 51KB | Downloads: 0
五彩黑白2323 2020-02-29 19:52:55
Description: BPSK demodulation program, written by Verilog
Plat: Verilog | Size: 1KB | Downloads: 1
五彩黑白2323 2020-02-29 19:51:38
Description: QPSK demodulation program, written by Verilog
Plat: Verilog | Size: 1KB | Downloads: 0
五彩黑白2323 2020-02-29 19:50:46
Description: 8PSK demodulation program, written in Verilog language
Plat: Verilog | Size: 7KB | Downloads: 0
五彩黑白2323 2020-02-29 19:49:43
Description: The demodulation program of 16QAM is written in Verilog language
Plat: Verilog | Size: 1KB | Downloads: 0
五彩黑白2323 2020-02-29 19:37:50
Description: Complete (7,4) Hamming decoding; verified by simulation
Plat: Verilog | Size: 4KB | Downloads: 0
五彩黑白2323 2020-02-29 19:31:25
Description: Ad9258 is an ADC chip, which realizes the configuration function of ad9258
Plat: Verilog | Size: 696KB | Downloads: 3
五彩黑白2323 2020-02-29 19:24:22
Description: Realize the configuration function of ad9117 chip, which is a DAC chip
Plat: Verilog | Size: 6KB | Downloads: 0
五彩黑白2323 2020-02-29 19:08:52
Description: The function of 32-bit accumulator is realized, and the signal bit width of external input is 32 bits
Plat: Verilog | Size: 3KB | Downloads: 1
五彩黑白2323 2020-02-29 19:07:37
Description: Implement the function of 32-bit adder
Plat: Verilog | Size: 3KB | Downloads: 0
hanshuibi 2020-02-29 15:40:09
Description: Verilog serial port code, including baud rate generation.
Plat: Verilog | Size: 2KB | Downloads: 0
fengya123xyn 2020-02-28 17:31:54
Description: 1000Hz square wave generation and Modelsim simulation
Plat: Others | Size: 115KB | Downloads: 1
SSaleem 2020-02-28 14:36:49
Description: Spartan 3 S200 project
Plat: Verilog | Size: 101KB | Downloads: 0
Murilo2486 2020-02-28 02:11:11
Description: A median filter designed using systemverilog
Plat: Verilog | Size: 38KB | Downloads: 0
l2tx 2020-02-27 23:48:31
Description: Xilinx ucf constraints for AD-DAC-FMC board
Plat: Others | Size: 234KB | Downloads: 0
l2tx 2020-02-27 23:44:32
Description: Arria 10 PMA settings for 10/40G PMA
Plat: Python | Size: 9KB | Downloads: 0
charrasy 2020-02-27 18:01:35
Description: FFT Implementation Code Based On VHDL
Plat: VHDL | Size: 54KB | Downloads: 1
KT猫 2020-02-27 15:27:29
Description: rsic-v cpu verilog project,and vcs simulation enviroment
Plat: Verilog | Size: 17457KB | Downloads: 2
风之火狐 2020-02-27 12:44:02
Description: Ad9361 data and configuration parameter document
Plat: Vivado | Size: 17651KB | Downloads: 9
蔺娇娇 2020-02-25 16:10:17
Description: This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.
Plat: Verilog | Size: 19146KB | Downloads: 1
年轻的国王 2020-02-25 11:18:27
Description: FPGA UART test code,simple and easy to study,good
Plat: Verilog | Size: 3447KB | Downloads: 3
年轻的国王 2020-02-25 11:17:02
Description: FPGA pll test code,simple and easy to study,good
Plat: Verilog | Size: 3001KB | Downloads: 0
年轻的国王 2020-02-25 11:15:30
Description: FPGA key test code,simple and easy to study,good
Plat: Verilog | Size: 2923KB | Downloads: 0
ww415 2020-02-24 23:01:58
Description: This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.
Plat: Verilog | Size: 71KB | Downloads: 2
ww415 2020-02-24 21:48:19
Description: This example is the implementation of an adder. Including the preparation of VCs and makefile files.
Plat: Others | Size: 1KB | Downloads: 0
小石呀 2020-02-24 16:02:31
Description: Obtain the correlation waveform through multiple rotations
Plat: VHDL | Size: 2KB | Downloads: 1
王晓007 2020-02-24 15:08:27
Description: This paper introduces the use of DDR3, including the establishment process of IP core in ISE and the explanation of key programs
Plat: Verilog | Size: 7046KB | Downloads: 1
千百万的精灵 2020-02-24 12:59:43
Description: Write two verilog programs to verify the difference between (b=a,c=b) and (b=a,c=b)
Plat: Verilog | Size: 4KB | Downloads: 0
千百万的精灵 2020-02-24 12:53:58
Description: LED control,control led lighting, water lamp control LED analog relay control
Plat: Verilog | Size: 3694KB | Downloads: 0
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