啊哈哈哈啊哈 2019-06-24 16:43:27
Description: The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.
Plat: Verilog | Size: 2403KB | Downloads: 1
Zwei99 2019-06-24 16:29:51
Description: Traffic light simulation
Plat: VHDL | Size: 24KB | Downloads: 0
869077989@qq.com 2019-06-23 21:11:24
Description: Method of Functional and Sequential Simulation with ModelSimSE (ALTERA) (2)
Plat: Others | Size: 857KB | Downloads: 0
869077989@qq.com 2019-06-23 21:02:56
Description: An Introduction to High Efficiency Tesbench Writing Method
Plat: VHDL | Size: 339KB | Downloads: 0
869077989@qq.com 2019-06-23 20:57:18
Description: Hello FPGA digital circuit classic series...
Plat: Quartus II | Size: 4241KB | Downloads: 1
kyzhou 2019-06-23 19:27:06
Description: Verilog program, which is used to control four AD7606 chips to achieve synchronous 32-channel 16-bit data acquisition of the FPGA program
Plat: Verilog | Size: 6KB | Downloads: 2
a1600225635 2019-06-22 22:25:57
Description: A signal assignment logic circuit is designed to assign 4-bit signal a to 4-bit signal B when the rising edge of clock signal arrives, and the original value of signal B to signal C.
Plat: Verilog | Size: 29KB | Downloads: 0
代码拾荒者 2019-06-22 18:10:11
Description: Simple and concise implementation of FSMC bus communication between FPGA and stm32
Plat: Verilog | Size: 3905KB | Downloads: 2
Mykinss 2019-06-22 15:14:48
Description: This is a complete digital logic and FPGA courseware, very suitable for beginners to learn.
Plat: C/C++ | Size: 72323KB | Downloads: 0
LuisGtz 2019-06-22 06:36:52
Description: controlador o modulo vga para fpga nexys 2 en vhdl
Plat: VHDL | Size: 423KB | Downloads: 0
strelizia 2019-06-21 18:10:20
Description: Serial peripheral experiment, the use of computer serial debugging tools to send data to the card, the card receives data, then data transmission back to the computer, and finally the use of computer serial debugging tools to display the data returned.
Plat: Verilog | Size: 3133KB | Downloads: 0
strelizia 2019-06-21 18:06:55
Description: Register: 4-bit bi-directional shift register 74194, the application of 4-bit bi-directional shift register 74194 register function.
Plat: Verilog | Size: 2995KB | Downloads: 0
fangpei 2019-06-21 17:33:58
Description: 8B/10Bencode and decoder
Plat: Verilog | Size: 6KB | Downloads: 0
Reha 2019-06-21 13:36:42
Description: Nucleo Board SPI example vhdl
Plat: Verilog | Size: 84KB | Downloads: 0
roc_verilog 2019-06-20 14:54:39
Description: MAX1437 interface logic
Plat: WINDOWS | Size: 467KB | Downloads: 1
roc_verilog 2019-06-20 14:53:25
Description: LVDS De-serialization
Plat: WINDOWS | Size: 20KB | Downloads: 1
roc_verilog 2019-06-20 14:51:12
Description: LVDS de-serialization
Plat: WINDOWS | Size: 1967KB | Downloads: 0
roc_verilog 2019-06-20 14:50:31
Description: LVDS de-serilization
Plat: WINDOWS | Size: 622KB | Downloads: 0
roc_verilog 2019-06-20 14:30:25
Description: TI TSW1250 FPGA code
Plat: WINDOWS | Size: 8200KB | Downloads: 1
是城还是废墟 2019-06-20 12:47:51
Description: The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.
Plat: VHDL | Size: 1596KB | Downloads: 2
zhangxiaoer 2019-06-20 11:08:09
Description: matlab code for tranformer
Plat: matlab | Size: 5KB | Downloads: 1
Metro 2019-06-20 09:56:36
Description: FT232H EEPROM Modify
Plat: C/C++ | Size: 621KB | Downloads: 7
铁心小男仆 2019-06-20 09:13:51
Description: Design of a 3-bit decimal digital frequency meter
Plat: Verilog | Size: 294KB | Downloads: 0
大神好大 2019-06-20 03:21:28
Description: The main function of the test program of FPGA is to light the running indicator.
Plat: VHDL | Size: 187KB | Downloads: 0
微风唐 2019-06-19 19:34:32
Description: Simulate the flashing of traffic lights,count down in 30 seconds interval and switch the color of the lights.
Plat: Quartus II | Size: 3341KB | Downloads: 0
Meysuan 2019-06-19 16:05:34
Description: Designing a 24-hour digital clock that can display hours, minutes, seconds and manually adjust ten minutes
Plat: VHDL | Size: 361KB | Downloads: 0
allhbj 2019-06-18 22:55:15
Description: usb2.0 device verilog
Plat: Verilog | Size: 201KB | Downloads: 1
cesc12345678 2019-06-18 21:16:10
Description: 512 bit package incentive generation module, data configurable, length configurable.
Plat: Verilog | Size: 4KB | Downloads: 0
Parsley 2019-06-18 12:18:10
Description: The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection
Plat: Verilog | Size: 1486KB | Downloads: 0
大东方ddf 2019-06-18 11:37:55
Description: ARM's official document on AXI protocol in AMBA protocol. It is suitable for ordinary designers to study and understand the bus protocol in depth.
Plat: Others | Size: 438KB | Downloads: 1
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