Qwerty909 2019-05-18 14:11:18
Description: Embedded SCM develop
Plat: Asm | Size: 450KB | Downloads: 0
star112 2019-05-17 21:33:53
Description: Bitcoin mining circuit in VHDL
Plat: WINDOWS | Size: 124KB | Downloads: 0
star112 2019-05-17 21:16:30
Description: AES algorithm implementation in VHDL.
Plat: WINDOWS | Size: 495KB | Downloads: 1
papabbb 2019-05-17 19:49:04
Description: The design guidance and programming environment of the FPGA are good references for the design of the FPGA.
Plat: Verilog | Size: 2129KB | Downloads: 0
zqqSuarez9 2019-05-17 16:49:57
Description: Verilog100 counter, hierarchy. Language or graphics top-level module.
Plat: Verilog | Size: 135KB | Downloads: 1
CoreYS 2019-05-17 00:23:27
Description: PS2 keyboard, FPGA external keyboard can achieve keyboard control, Verilog language writing, you can take away what you need.
Plat: Verilog | Size: 24803KB | Downloads: 1
frontosa 2019-05-16 23:11:01
Description: High-Definition Multimedia Interface (HDMI) IP Core User Guide
Plat: Verilog | Size: 532KB | Downloads: 1
dahabilmiyorum 2019-05-16 15:06:39
Description: zedboard master xdc file
Plat: Verilog | Size: 3KB | Downloads: 0
红蓝心 2019-05-16 11:37:11
Description: An example of UART serial port protocol based on FPGA to realize loopback transmission
Plat: Verilog | Size: 849KB | Downloads: 0
1219684412 2019-05-16 10:47:51
Description: Realization of RS232 Serial Communication on FPGA Using Verilog Language
Plat: Verilog | Size: 530KB | Downloads: 2
1219684412 2019-05-16 10:44:54
Description: On the FPGA, read-write test of SRAM is implemented by Verilog language
Plat: Verilog | Size: 538KB | Downloads: 0
sy3027 2019-05-16 08:52:16
Description: Use SPI protocol to read, write and erase FLASH
Plat: Verilog | Size: 56568KB | Downloads: 0
槊哥 2019-05-15 21:32:33
Description: IIC Protocol Code for Acceleration Sensor MPU6050
Plat: VHDL | Size: 2KB | Downloads: 0
cjhcjh 2019-05-15 20:42:27
Description: A 16-bit CPU sent by a teacher has basic functions
Plat: VHDL | Size: 2085KB | Downloads: 0
sublime 2019-05-15 17:19:21
Description: fpga adc high-speed 50mhz
Plat: VHDL | Size: 5256KB | Downloads: 0
hiepvq 2019-05-15 14:26:11
Description: Create 4 to 8 way, viterbi decoder
Plat: Verilog | Size: 9KB | Downloads: 1
she_rry 2019-05-15 10:36:31
Description: VHDL 2-4 decoder, can be related to the decoding, pro-test available
Plat: VHDL | Size: 145KB | Downloads: 0
shimadaneko 2019-05-15 09:07:03
Description: basic decoder, encoder, mux, priority encoder code and testbench
Plat: Verilog | Size: 3378KB | Downloads: 0
jkjkjkjkjk 2019-05-14 17:17:15
Description: In the digital transmission system, because of the existence of noise, channel fading and other interference factors, the transmission signal will be wrong, resulting in error code. Although channel coding and redundancy of transmission codes are increased in order to prevent errors in digital signal transmission, such as increasing supervisory bits, to overcome errors in channel transmission, this error detection and correction capability is limited. For example, when a burst error occurs and a large number of errors occur, the channel error correction is powerless. Convolutional interleaver can scramble the original information code. In spite of large-scale burst errors, these can be dispersed by de-interleaver, so that large-scale errors can be more evenly distributed to different code segments, which is conducive to the realization of channel error correction.
Plat: Verilog | Size: 367KB | Downloads: 1
xyhwsad666 2019-05-14 14:42:15
Description: It's OV7670 camera that collects images and displays them in real time through TFT.
Plat: VHDL | Size: 15042KB | Downloads: 0
xyhwsad666 2019-05-14 14:35:49
Description: It is to read the data in SD card and display it by LCD
Plat: VHDL | Size: 12305KB | Downloads: 3
xyhwsad666 2019-05-14 14:32:32
Description: AX301 AX430 Test Program Displays Color Bars
Plat: VHDL | Size: 3770KB | Downloads: 0
逍遥离歌欠 2019-05-14 11:00:24
Description: State-based VGA display
Plat: C/C++ | Size: 818KB | Downloads: 0
jjjjaa 2019-05-14 10:49:09
Description: Wireless communication experiment program
Plat: Verilog | Size: 9KB | Downloads: 0
donge2019 2019-05-14 00:55:54
Description: The Digilent Cmod S6 is a small, 48-pin DIP form factor board built around a Xilinx Spartan 6 LX4 FPGA. The board also includes a programming ROM, clock source, USB programming and data transfer circuit, power supplies, and basic I/O devices. There are 46 FPGA I/O signals that are routed to 100-mil-spaced through-hole pins, making the Cmod S6 well suited for use with solderless breadboards. At just .7" by 2.6" inches, it can also be loaded in a standard socket and used in embedded systems.
Plat: VHDL | Size: 1035KB | Downloads: 0
小白呜呜呜 2019-05-13 22:05:27
Description: The PCB board has a PCB diagram of the amplification filter circuit and the data.
Plat: VHDL | Size: 14172KB | Downloads: 0
小白呜呜呜 2019-05-13 21:54:31
Description: FPGA documentation on configuration clocks, IO resources, package and pin specifications, and PCB package.
Plat: VHDL | Size: 4790KB | Downloads: 0
d7oom 2019-05-13 18:24:45
Description: catalog of new intel fpga devices
Plat: WINDOWS | Size: 14066KB | Downloads: 0
d7oom 2019-05-13 18:21:04
Description: agilex fpga description
Plat: WINDOWS | Size: 334KB | Downloads: 0
yuan0911 2019-05-13 12:22:13
Description: 7-story elevator control program, double elevator The implementation of the seven-story elevator scheduling algorithm written in VHDL language. The simulation was successful.
Plat: VHDL | Size: 47KB | Downloads: 0