nicozhang 2019-06-29 23:13:42
Description: The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture
Plat: Others | Size: 8046KB | Downloads: 4
荷叶蓝 2019-06-29 14:13:44
Description: This program mainly uses Verilog to realize UART to SPI interface function, including UART core code, SPI controller code and conversion control code, which is very suitable for FPGA coders to develop reference and reduce development time.
Plat: Verilog | Size: 1282KB | Downloads: 0
matin007 2019-06-29 01:08:09
Description: LTE is an abbreviation for Long Term Evolution.
Plat: LINUX | Size: 653KB | Downloads: 0
shan928 2019-06-28 20:32:36
Description: fpga controlled adc 7768
Plat: VHDL | Size: 960KB | Downloads: 0
sikimichin 2019-06-28 19:01:04
Description: most be so fun to have resorted data i fir
Plat: C++ Builder | Size: 90KB | Downloads: 0
chengzhibi 2019-06-28 15:18:09
Description: A program for the lantern can be lit one by one according to the requirements.
Plat: Quartus II | Size: 220KB | Downloads: 1
younhaa 2019-06-28 12:04:14
Description: Set time, school time, time, alarm clock
Plat: Quartus II | Size: 2542KB | Downloads: 2
电子信息小菜鸡 2019-06-28 09:09:47
Description: Master's thesis on FPGA digital down conversion design in Xi'an University of Electronic Science and Technology
Plat: Verilog | Size: 13184KB | Downloads: 1
电子信息小菜鸡 2019-06-28 09:06:33
Description: I have collected good papers on FPGA digital down conversion
Plat: Verilog | Size: 4485KB | Downloads: 0
NANA7878 2019-06-27 17:11:46
Description: Verilog Implementation of Several Simple Functions in Digital Logic Design
Plat: Verilog | Size: 2622KB | Downloads: 0
Arhangel 2019-06-27 15:55:06
Description: Finished state machine and Clock data recovery
Plat: Verilog | Size: 225KB | Downloads: 0
平东将军 2019-06-27 14:19:36
Description: Controlling MAX5250 Chip
Plat: Verilog | Size: 1KB | Downloads: 0
naveen423 2019-06-27 13:38:26
Description: SPI Doc used for depeleoping SPI
Plat: VHDL | Size: 432KB | Downloads: 0
kyros1972 2019-06-26 21:51:16
Description: PWM-Example for VHDL
Plat: VHDL | Size: 2997KB | Downloads: 0
kyros1972 2019-06-26 21:49:37
Description: Implementation of UART in VHDL
Plat: VHDL | Size: 3599KB | Downloads: 0
kyros1972 2019-06-26 21:39:01
Description: Blynk LED by DE0-Nano
Plat: VHDL | Size: 3118KB | Downloads: 0
dengcong 2019-06-26 20:29:33
Description: Digital tube, buzzer, button and LED lamp are used to make electronic clock, which can be calibrated by button.
Plat: Verilog | Size: 3836KB | Downloads: 0
hello_tr 2019-06-26 17:46:45
Description: The program implements a comparator that inputs two numbers, compares them, and outputs the results.
Plat: Verilog | Size: 33KB | Downloads: 1
静默。 2019-06-26 15:51:53
Description: Implementation of FFT algorithm based on FPGA
Plat: C/C++ | Size: 48376KB | Downloads: 4
undef 2019-06-26 12:27:30
Description: all the firmware patch ready for the usage tr
Plat: LINUX | Size: 38KB | Downloads: 0
搭错车 2019-06-26 11:35:00
Description: Realization of CPU composition and simulation test
Plat: Verilog | Size: 166KB | Downloads: 1
chengruiqi 2019-06-25 16:41:22
Description: Official simulation model facilitates debugging and simulation
Plat: Verilog | Size: 1634KB | Downloads: 0
Cosecant- 2019-06-25 15:54:05
Description: Implementation of RISC-V CPU Decoder
Plat: Verilog | Size: 2KB | Downloads: 0
zkylsf 2019-06-25 15:07:38
Description: 4 PWM wave inverter VHDL program
Plat: Quartus II | Size: 61KB | Downloads: 1
zkylsf 2019-06-25 15:02:25
Description: FPGA/CPLD program frequency 50kHz phaseshift
Plat: Quartus II | Size: 2592KB | Downloads: 1
zkylsf 2019-06-25 14:59:18
Description: output 20-100kHZ PWM signal ...
Plat: Quartus II | Size: 74KB | Downloads: 0
zkylsf 2019-06-25 14:55:33
Description: TLC549 AD transform LED display
Plat: Quartus II | Size: 426KB | Downloads: 0
zkylsf 2019-06-25 14:51:54
Description: LED verilog 8 legs display Verilog
Plat: Quartus II | Size: 121KB | Downloads: 1
liuphonix 2019-06-25 13:43:28
Description: XILINX 7 series selection guide
Plat: VHDL | Size: 589KB | Downloads: 0
aphat 2019-06-24 17:56:37
Description: rtc program,have been verified
Plat: Verilog | Size: 4KB | Downloads: 0
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