小梅哥fpga 2020-03-12 18:12:38
Description: The calculator based on Verilog uses matrix keyboard to input data and digital tube to display the operation process and results. The development board based on little mac620 passed the verification
Plat: Verilog | Size: 40KB | Downloads: 0
小梅哥fpga 2020-03-12 18:09:57
Description: The taximeter written by Verilog has passed the test run on the ac620 development board of xiaomeige.
Plat: Verilog | Size: 190KB | Downloads: 0
小梅哥fpga 2020-03-12 18:06:21
Description: The controller for managing the MDIO interface of Ethernet PHY written by Verilog has been verified on the development boards ac620 and ac6102 of xiaomeige, and can successfully set the link speed of phy chip to the specified speed.
Plat: Verilog | Size: 3KB | Downloads: 1
Verdvana 2020-03-11 22:44:00
Description: Implementation of 8B / 10B coding Verilog
Plat: Verilog | Size: 101KB | Downloads: 0
Verdvana 2020-03-11 22:29:47
Description: Bit width and number customizable FFT module of base 2
Plat: Verilog | Size: 214KB | Downloads: 0
q落羽 2020-03-11 21:29:11
Description: Xilinx ise license Collection, including Vivado and ISE cracking licenses. After ISE is installed, the loading license can be completed, which is the most complete device library.
Plat: Others | Size: 6KB | Downloads: 1
vvrobinham 2020-03-11 18:36:21
Description: Verilog 2001 standard,IEEE1364-2001 version Digital IC / FPGA Hardware Describe Language, Standard for FPGA/Digital IC design.
Plat: Verilog | Size: 2128KB | Downloads: 0
liyan2020 2020-03-11 15:40:45
Description: LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac
Plat: VHDL | Size: 1KB | Downloads: 5
qwe12121 2020-03-11 09:33:24
Description: This program uses rc522 for stm32f407, which is the access control system. It has card number reading and new card writing, and uses serial port to watch
Plat: C/C++ | Size: 7KB | Downloads: 0
Crypps 2020-03-11 04:48:32
Description: excellent document from xilinx
Plat: R language | Size: 1727KB | Downloads: 0
Crypps 2020-03-11 04:46:34
Description: interesting document of xilinx website you need it
Plat: Verilog | Size: 387KB | Downloads: 0
jianyunshixi 2020-03-10 22:15:06
Description: Through vivado, the 16 bit running water lamp can flash in order, and the simulation waveform can be displayed
Plat: Vivado | Size: 669KB | Downloads: 0
jianyunshixi 2020-03-10 21:45:56
Description: The 38 decoder is realized by vivado, and the corresponding output is realized by different input. The low level is effective
Plat: Verilog | Size: 118KB | Downloads: 0
super123321 2020-03-10 14:11:30
Description: a test for vivado learn how to use microblaze
Plat: C/C++ | Size: 7239KB | Downloads: 0
xian636355 2020-03-10 10:47:31
Description: About the RGB driver of ws2812, I hope it can help
Plat: C/C++ | Size: 1KB | Downloads: 0
c1022 2020-03-09 19:21:10
Description: Simple clock, hour to 23, minute to 59, i.e. clear at 24:00
Plat: Quartus II | Size: 3372KB | Downloads: 0
c1022 2020-03-09 19:19:24
Description: The traffic lights of single intersection, red, green and yellow will change to the next color after how many seconds
Plat: Quartus II | Size: 3399KB | Downloads: 0
逍遥大侠 2020-03-09 17:53:44
Description: Verilog HDL lights up 4.3-inch TFT, displaying color bar picture
Plat: Verilog | Size: 3284KB | Downloads: 0
IrisL 2020-03-09 17:02:08
Description: A series of foreign electronic and communication textbooks Verilog HDL digital design
Plat: Verilog | Size: 13188KB | Downloads: 2
albumis 2020-03-09 15:58:27
Description: The simplified SPI master-slave code written by Verilog is used to expand the port.
Plat: Others | Size: 13799KB | Downloads: 0
全新国 2020-03-09 14:51:57
Description: The FIFO function is realized with the IP core of FPGA, and the read-write operation is completed
Plat: Quartus II | Size: 6091KB | Downloads: 0
ilsehisa 2020-03-09 11:23:46
Description: Binocular ranging system based on FPGA real-time processing (project)
Plat: Quartus II | Size: 354KB | Downloads: 0
ilsehisa 2020-03-09 11:18:23
Description: CAN bus controls IP core
Plat: Quartus II | Size: 135KB | Downloads: 2
熬过去 2020-03-08 20:01:36
Description: Verilog design points
Plat: C/C++ | Size: 4729KB | Downloads: 0
1003512666 2020-03-08 19:17:26
Description: This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the entire folder. After decompression, it can be run directly on quartus 13.0.
Plat: Quartus II | Size: 5514KB | Downloads: 1
muxiaoxiao 2020-03-08 18:52:32
Description: The definition and application of PAC learnable in machine learning. Very important basic knowledge.
Plat: VHDL | Size: 1026KB | Downloads: 0
AvatarGanemede 2020-03-08 18:40:13
Description: FPGA experiment: countdown device, which can count from the given number to 0
Plat: Others | Size: 455KB | Downloads: 0
阿诺s 2020-03-08 18:05:05
Description: Ethernet three mode IP core, used for 1000M network communications, including source code.
Plat: Verilog | Size: 3125KB | Downloads: 0
飞天1983 2020-03-08 12:28:10
Description: RS485 read-write driver written by Verilog
Plat: Verilog | Size: 3405KB | Downloads: 0
苦大 2020-03-07 20:54:26
Description: Xia Yuwen - Verilog classic course third edition, single chip microcomputer
Plat: PDF | Size: 1295KB | Downloads: 1
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