可樂啊 2019-06-16 20:29:36
Description: Simple multiplier, can carry out simple multiplication, simulation in Modelsim is correct
Plat: Verilog | Size: 38KB | Downloads: 0
AerF 2019-06-16 16:03:35
Description: 8x8 matrix multiplication, variable bit width.
Plat: Verilog | Size: 1KB | Downloads: 0
神界 2019-06-16 15:50:06
Description: Implement minute-second timing (keyless)
Plat: Verilog | Size: 1355KB | Downloads: 0
freshinverilog 2019-06-16 11:55:32
Description: Three Simple Experimental Source Programs
Plat: VHDL | Size: 35706KB | Downloads: 0
KLWG 2019-06-15 13:47:19
Description: Press button 1 to write the data, then press button 0 to read the data, and with LED flickering constantly, prompting the program to run. The program starts to detect whether W25Q128 exists or not. If it does not exist, it will display error information on TFTLCD module, and LED will flash slowly.
Plat: ansys | Size: 3KB | Downloads: 0
Nay95 2019-06-14 22:50:10
Description: test my upload this code is switch for LED
Plat: Verilog | Size: 115KB | Downloads: 0
quanghochoi 2019-06-14 16:59:04
Description: counter verilog code
Plat: WINDOWS | Size: 4213KB | Downloads: 0
保定赵先生 2019-06-14 11:45:39
Description: fpga red and write sd card with the help of spi
Plat: Verilog | Size: 5058KB | Downloads: 0
springrain1 2019-06-14 09:18:30
Description: Gauss Filtered Minimum Shift Keying is a modulation method used in GSM system. Digital modem technology is an important part of air interface of digital cellular mobile communication system. GMSK modulation is a method of inserting a Gaussian low-pass pre-modulation filter before the MSK (minimum frequency shift keying) modulator. GMSK improves the spectrum utilization and communication quality of digital mobile communication.
Plat: matlab | Size: 3KB | Downloads: 0
springrain1 2019-06-14 09:16:40
Description: Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.
Plat: matlab | Size: 1KB | Downloads: 0
springrain1 2019-06-14 09:10:59
Description: Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.
Plat: WINDOWS | Size: 1KB | Downloads: 0
jinji 2019-06-13 14:11:56
Description: PCI-express DMA driver for Xilinx linux
Plat: C/C++ | Size: 485KB | Downloads: 0
龍之龍 2019-06-13 14:11:49
Description: Using vivado to write FPGA code for sequence detection, the attachment gives the specific state machine structure, as well as the prompt of the file.
Plat: VHDL | Size: 193KB | Downloads: 1
shatao 2019-06-12 20:14:17
Description: Semi-adder implementation, simple semi-adder, as a novice experiment
Plat: Verilog | Size: 2960KB | Downloads: 0
tanshi706 2019-06-12 16:38:05
Description: Ultrasound ranging, after ranging through digital tube display, led and buzzer alarm through different distances
Plat: Verilog | Size: 6311KB | Downloads: 0
a123sun 2019-06-12 09:21:31
Description: The test routine of the development of the FPGA for 7035 board can grasp the basic of the introduction of the FPGA well.
Plat: C/C++ | Size: 3682KB | Downloads: 0
a123sun 2019-06-12 09:12:03
Description: A tutorial on the development of FPGA, including development manuals and source code, has complete routines and good learning materials for FPGA.
Plat: C/C++ | Size: 17223KB | Downloads: 1
serri57 2019-06-12 01:45:53
Description: examples about vhdl compartor
Plat: Verilog | Size: 10KB | Downloads: 0
serri57 2019-06-12 01:43:21
Description: examples about vhdl combination
Plat: VHDL | Size: 20KB | Downloads: 2
甄小疯 2019-06-11 19:21:39
Description: Seventy-four voters, seven keys, when the keys are greater than or equal to four, the LED lights come on
Plat: Quartus II | Size: 6459KB | Downloads: 0
甄小疯 2019-06-11 19:17:45
Description: The digital tube is refreshed dynamically to display the number of keys. When the keys change, the reality of the digital tube changes.
Plat: Quartus II | Size: 4282KB | Downloads: 0
甄小疯 2019-06-11 19:15:12
Description: Digital Clock, FPGA Display Clock, Variable Control Clock
Plat: Quartus II | Size: 3169KB | Downloads: 2
nie111 2019-06-11 17:49:53
Description: EMIO example in vivado, which has detailed configuration of VIVADO, and detailed code in SDK!
Plat: VHDL | Size: 6069KB | Downloads: 0
逍遥大哥 2019-06-11 10:11:09
Description: The UDP data transmission instance of the FPGA is tested to be effective and suitable for data transmission between the FPGA and PC or ARM.
Plat: C++ | Size: 47KB | Downloads: 2
wdtlm 2019-06-10 22:22:11
Description: Realize function, task and system monitoring in Verilog
Plat: Verilog | Size: 136KB | Downloads: 0
wdtlm 2019-06-10 22:20:07
Description: Realize the basic HDL code of 2-1 in Verilog
Plat: Verilog | Size: 4KB | Downloads: 0
wdtlm 2019-06-10 22:18:42
Description: The basic case statement, if statement and while statement in Verilog are implemented.
Plat: Verilog | Size: 566KB | Downloads: 0
wdtlm 2019-06-10 22:16:37
Description: Verilog code for multiplication operation
Plat: Verilog | Size: 1040KB | Downloads: 0
wdtlm 2019-06-10 22:14:31
Description: Verilog code for basic arithmetic operation
Plat: Verilog | Size: 137KB | Downloads: 0
wdtlm 2019-06-10 22:11:54
Description: Implementation of Verilog code for 4-bit semi-adde
Plat: Verilog | Size: 252KB | Downloads: 0
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