陈瑞 2005-02-15 16:46:24
Description: with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.
Plat: C/C++ | Size: 1KB | Downloads: 14
廖啟仲 2005-02-15 13:14:09
Description: i2c to os/2
Plat: C/C++ | Size: 20KB | Downloads: 7
毛毛虫1 2005-02-03 15:19:01
Description: 1:1 generic-frequency module
Plat: MultiPlatform | Size: 1KB | Downloads: 18
美丽江河水 2005-01-31 20:54:00
Description: This is my calculation prepared by the sub- PLL frequency of a tool
Plat: C++ Builder | Size: 848KB | Downloads: 40
jiayu 2005-01-31 09:10:23
Description: LED LCD used small program
Plat: Asm | Size: 18KB | Downloads: 14
李恒 2005-01-30 20:36:47
Description: USB1.1 IP core for device control, written with hardware describing language of Verilog.
Plat: Others | Size: 128KB | Downloads: 175
安鹏洲 2005-01-27 20:19:20
Description: the VHDL-ahead Adder
Plat: Others | Size: 42KB | Downloads: 970
lzw 2005-01-27 17:59:48
Description: access to the procedure cpu id
Plat: Visual C++ | Size: 10KB | Downloads: 70
李长武 2005-01-27 16:05:31
Description: obtained cpu usage
Plat: Visual C++ | Size: 13KB | Downloads: 224
崔广辉 2005-01-27 13:33:56
Description: VHDL basic arithmetic library
Plat: MultiPlatform | Size: 242KB | Downloads: 56
firstspace 2005-01-27 12:12:04
Description: useful VHDL source code
Plat: TEXT | Size: 577KB | Downloads: 20
唐林 2005-01-27 10:02:22
Description: This is compatible CPU 8051 VHDL, it is not a tort. God bless!
Plat: Unix_Linux | Size: 34KB | Downloads: 160
李翔 2005-01-23 16:25:38
Description: control procedures, coordination of memory, cpu cache operation between straight
Plat: C/C++ | Size: 1KB | Downloads: 5
wheragon 2005-01-21 08:57:30
Description: AU 5.6 LCD Datasheet
Plat: PDF | Size: 208KB | Downloads: 14
张庆辉 2005-01-20 14:52:14
Description: four Multiplier VHDL source
Plat: MultiPlatform | Size: 1KB | Downloads: 86
张庆辉 2005-01-20 14:50:38
Description: four division of VHDL source
Plat: MultiPlatform | Size: 1KB | Downloads: 31
张庆辉 2005-01-20 14:35:18
Description: 16 parallel with the VHDL-related procedures
Plat: MultiPlatform | Size: 1KB | Downloads: 58
张庆辉 2005-01-20 14:16:31
Description: pulse Doppler radar echo signal coherent accumulation of VHDL source
Plat: MultiPlatform | Size: 2KB | Downloads: 99
张庆辉 2005-01-20 13:51:10
Description: program in VHDL language for generating pseudo-random m sequence
Plat: MultiPlatform | Size: 2KB | Downloads: 205
张楠 2005-01-19 00:26:17
Description: locks VHDL procedures
Plat: Windows_Unix | Size: 1KB | Downloads: 63
胡显辉 2005-01-18 17:58:18
Description: Verilog source 9.rar
Plat: WINDOWS | Size: 1KB | Downloads: 4
胡显辉 2005-01-18 17:57:50
Description: Verilog source 10.rar
Plat: WINDOWS | Size: 1KB | Downloads: 4
胡显辉 2005-01-18 17:56:34
Description: Verilog source 13.rar
Plat: WINDOWS | Size: 38KB | Downloads: 6
胡显辉 2005-01-18 17:50:11
Description: Verilog source 14.rar
Plat: WINDOWS | Size: 9KB | Downloads: 35
王刚 2005-01-18 02:49:29
Description: IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Plat: C/C++ | Size: 372KB | Downloads: 39
熊辉波 2005-01-13 13:23:24
Description: VHDL hardware description language operations
Plat: C/C++ | Size: 69KB | Downloads: 21
熊辉波 2005-01-13 13:19:33
Description: a two-way bus VHDL achieve
Plat: C/C++ | Size: 25KB | Downloads: 74
熊辉波 2005-01-13 13:18:44
Description: synchronous reset signal with the two-frequency VHDL procedures
Plat: C/C++ | Size: 2KB | Downloads: 20
熊辉波 2005-01-13 13:16:54
Description: VHDL Storage/counter design
Plat: C/C++ | Size: 6KB | Downloads: 16
熊辉波 2005-01-13 13:15:56
Description: full adder VHDL simulation program and
Plat: C/C++ | Size: 86KB | Downloads: 25
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