李无志 2005-05-02 20:10:07
Description: famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
Plat: Others | Size: 649KB | Downloads: 371
李无志 2005-05-02 20:08:11
Description: This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
Plat: Others | Size: 93KB | Downloads: 40
安德森 2005-04-30 13:48:24
Description: own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,
Plat: MultiPlatform | Size: 3KB | Downloads: 16
阿乐 2005-04-25 15:00:32
Description: modelsim simulation using a sine wave generated procedures
Plat: Windows_Unix | Size: 67KB | Downloads: 229
阿乐 2005-04-25 14:59:31
Description: NiosII_Exercises_Ver3,this niosII 3.o for cyclone
Plat: Windows_Unix | Size: 1378KB | Downloads: 29
阿乐 2005-04-25 14:57:22
Description: made a ModelSim simulation based on the Verilog source code
Plat: Windows_Unix | Size: 73KB | Downloads: 59
陆阳 2005-04-24 15:30:57
Description: a simple 8 cpu to achieve the functions, from the outside into binary, simulating the operation of cpu
Plat: C++ | Size: 48KB | Downloads: 34
闪核 2005-04-21 14:52:32
Description: for testing the water ACEX1k30 lights procedures, the frequency of 20MHz crystal oscillator. Operating environment FLEX10K
Plat: Others | Size: 124KB | Downloads: 13
czy 2005-04-21 08:12:57
Description: Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Plat: matlab | Size: 302KB | Downloads: 199
czy 2005-04-21 08:08:43
Description: most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced multi-purpose microcontroller core or RSIC microcontroller and microprocessor applications SOC very valuable reference
Plat: matlab | Size: 208KB | Downloads: 319
czy 2005-04-21 08:04:15
Description: described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Plat: matlab | Size: 480KB | Downloads: 823
wicy001 2005-04-19 13:13:55
Description: This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Plat: MultiPlatform | Size: 5KB | Downloads: 78
qllaoda 2005-04-18 13:59:06
Description: Lattice Store, the Chinese character LCD display so essential
Plat: MultiPlatform | Size: 109KB | Downloads: 279
刘韶光 2005-04-18 10:23:32
Description: QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram
Plat: C/C++ | Size: 75KB | Downloads: 373
波波 2005-04-16 20:59:35
Description: RS232 data transmitter, suitable for beginners VHDL reference
Plat: Others | Size: 4KB | Downloads: 82
刘卫 2005-04-16 12:55:03
Description: use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
Plat: Windows_Unix | Size: 345KB | Downloads: 173
刘卫 2005-04-16 12:48:15
Description: digit passwords detonated's input Description : one at the start and enter the password before the wait state, according to First READY button, now ready to be imported into digital code; Two, when detonated after the incident, should wait for the state to set up WAIT_T bond; three, if a password is not correct, this time to operate READY WAIT_T and is non-functional, the design must be re-installed to wait for the state, set up SETUP button SETUP internal keys, the operator should not contact; 4 to determine the password, to design a FIRE- ignition keys;
Plat: Windows_Unix | Size: 24KB | Downloads: 33
jinker 2005-04-15 16:45:36
Description: Hitachi SH-2 CPU core VERLOG source can be integrated in ISE6, documentation,
Plat: Others | Size: 1064KB | Downloads: 16
陆文娟 2005-04-15 14:43:24
Description: program vending machine at the core function, with three kinds of commodity prices, the number of choice, having to function.
Plat: Windows_Unix | Size: 2KB | Downloads: 42
2005-04-14 15:45:24
Description: curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Plat: PHP | Size: 141KB | Downloads: 678
郭慧勤 2005-04-13 17:15:23
Description: a simple microprocessor to achieve, for several common to the operation of the computer for those familiar with the working principle helpful, and with the detailed design reports and design ideas. The word is the final document source code.
Plat: C/C++ | Size: 438KB | Downloads: 124
张念华 2005-04-13 10:30:36
Description: VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
Plat: Unix_Linux | Size: 1KB | Downloads: 18
星麒麟 2005-04-11 16:36:43
Description: simple electronic toys perception module programming, through external input signal a change in the internal signal. In order to change the state of toys
Plat: MultiPlatform | Size: 1KB | Downloads: 12
余飞 2005-04-07 19:56:36
Description: VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
Plat: MultiPlatform | Size: 7KB | Downloads: 114
陈旭 2005-04-06 19:51:06
Description: FFT IP core of the source code for VHDL ~
Plat: C/C++ | Size: 31KB | Downloads: 288
陈旭 2005-04-06 19:43:43
Description: using VHDL on the CPLD Serial Communication
Plat: C/C++ | Size: 4KB | Downloads: 58
陈旭 2005-04-06 19:42:40
Description: using VHDL prepared a simple UART
Plat: C/C++ | Size: 3KB | Downloads: 22
陈旭 2005-04-06 19:41:14
Description: prepared using VHDL paragraph 107 of the procedures Digital Display
Plat: C/C++ | Size: 1KB | Downloads: 37
路路 2005-04-06 19:36:56
Description: Computer Architecture Handbook on Verilog HDL
Plat: Others | Size: 65KB | Downloads: 16
孙文福 2005-04-04 11:32:31
Description: This paper describes the use of Verilog hardware design language, the basic skills
Plat: C/C++ | Size: 8KB | Downloads: 83
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