吴毅 2005-10-17 01:00:30
Description: Configurable cpu core that supports Z80, 8080 and gameboy instruction sets
Plat: MultiPlatform | Size: 41KB | Downloads: 14
凌燕 2005-10-13 20:13:23
Description: 65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process
Plat: Windows_Unix | Size: 3KB | Downloads: 625
开心火 2005-10-13 15:00:41
Description: This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
Plat: Windows_Unix | Size: 1650KB | Downloads: 37
male 2005-10-13 14:43:50
Description: from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
Plat: Windows_Unix | Size: 4KB | Downloads: 4
陈旭 2005-10-12 14:18:35
Description: The source code of PCI VHDL.
Plat: Others | Size: 3KB | Downloads: 183
roya 2005-10-11 22:21:34
Description: 4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to learn.
Plat: matlab | Size: 3KB | Downloads: 21
周小川 2005-10-11 15:52:05
Description: convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Plat: MultiPlatform | Size: 248KB | Downloads: 357
蔡怡俊 2005-10-08 06:57:17
Description: CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
Plat: C/C++ | Size: 213KB | Downloads: 62
好 哥哥 2005-10-05 23:53:01
Description: NIC status test procedure card can be made of the physical information. The good kind.
Plat: Visual C++ | Size: 92KB | Downloads: 16
lfq 2005-09-27 23:22:10
Description: SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
Plat: MultiPlatform | Size: 6KB | Downloads: 324
站长 2005-09-27 20:03:31
Description: Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
Plat: Windows_Unix | Size: 637KB | Downloads: 46
站长 2005-09-27 19:42:07
Description: Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit
Plat: Windows_Unix | Size: 329KB | Downloads: 41
站长 2005-09-27 19:38:34
Description: Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divide is three parts: The sampling electric circuit, the gate control the electric circuit and the decoding circuit
Plat: Windows_Unix | Size: 64KB | Downloads: 26
站长 2005-09-27 19:34:01
Description: This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC) and the picture element positional information; Another receive picture element positional information, and output color signal. Like this is advantageous for carries on the graph to revise, simultaneously is also easy to realize
Plat: Windows_Unix | Size: 896KB | Downloads: 19
joan 2005-09-25 14:18:05
Description: software designers Watchable UART reference design
Plat: Windows_Unix | Size: 93KB | Downloads: 78
joan 2005-09-25 14:14:55
Description: VHDL examples examples to learn VHDL programming
Plat: Windows_Unix | Size: 76KB | Downloads: 16
游畅 2005-09-24 18:55:41
Description: this procedure code decoder VHDL hardware is used to prepare the language.
Plat: WORD | Size: 3KB | Downloads: 87
阿兰 2005-09-21 18:33:28
Description: this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
Plat: Others | Size: 1KB | Downloads: 15
杨云丰 2005-09-19 11:19:36
Description: des encryption algorithm to achieve the Verilog language
Plat: Windows_Unix | Size: 66KB | Downloads: 264
真名 2005-09-17 18:54:13
Description: James Armstrong VHDL Design , source code
Plat: Unix_Linux | Size: 45KB | Downloads: 109
imljg 2005-09-17 09:41:16
Description: VHDL digital display program development environment for Xilinx ISE Integrated Development Tools
Plat: Others | Size: 1KB | Downloads: 18
xfeng 2005-09-16 16:40:58
Description: A Chinese introduction to quartus II.
Plat: Windows_Unix | Size: 3017KB | Downloads: 123
鄧翀 2005-09-15 23:12:27
Description: a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on. I run a simulator, marking the connecting pin. I next tried in a circuit board, there is no problem. Experimental use of the board brothers put CLK1 TESTOUT3 changed to a chorus or 0. Newcomers line help is everyone's responsibility.
Plat: Windows_Unix | Size: 231KB | Downloads: 146
司法 2005-09-15 11:34:36
Description: I2C bus contrll functions implemented by Verilog HDL.
Plat: Unix_Linux | Size: 869KB | Downloads: 207
SEEEEEEEE 2005-09-14 23:35:04
Description: through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasions.
Plat: Windows_Unix | Size: 1KB | Downloads: 37
张雷 2005-09-13 11:34:09
Description: USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements
Plat: Others | Size: 489KB | Downloads: 127
刘建华 2005-09-11 14:48:54
Description: i2c interrupt request Control c programming language source code procedures
Plat: C/C++ | Size: 83KB | Downloads: 18
杨要强 2005-09-11 09:57:14
Description: 7topic http://www.edacn.net/cgi-bin/forums.cgi forum = = 9127, under R3 R0 to the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 to R0 the output signal C0 to C3 with the scanning signal jointly decided that button is pressed. the idea of the preparation of VHDL : external interfaces include : a. INPUT feet : CLK, R3 ~ R0. b. feet OUTPUT : C0 to C3, DATA3 ~ DATA0 (identify the key values ).
Plat: MultiPlatform | Size: 1523KB | Downloads: 9
杨要强 2005-09-11 09:46:27
Description: scan signal from C0 to C3 into the signal in order of 1000-gt; 0100- gt; 0010- gt; 0001- gt; 1000 cycle, when the scanning signal to 1000, then scanning 0 line of four keys. Scanning signal for 0100, then scanning resolution a line of four buttons, and so on. if a button is pressed, R3 ~ R0 the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 ~ R0 with the output signal of C0 to C3
Plat: MultiPlatform | Size: 110KB | Downloads: 6
话正 2005-09-09 14:37:08
Description: 20 interface circuit using Verilog programming, fully integrated
Plat: Unix_Linux | Size: 80KB | Downloads: 301
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