聂联合开发 2019-05-02 16:56:35
Description: Frequency Meter Based on FPGA and Digital Tube Display the Frequency to be Measured
Plat: VHDL | Size: 1349KB | Downloads: 0
hanziG 2019-05-02 09:01:12
Description: The basic gate circuits, and gates, non-gates, exclusive or gates, and non-gates, or gates, and non-gates can be implemented in a case-by-case manner.
Plat: VHDL | Size: 23400KB | Downloads: 0
SEXYLADY 2019-05-01 22:12:15
Description: The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the data range of simulation weight in the operation process is required.
Plat: matlab | Size: 928KB | Downloads: 0
SEXYLADY 2019-05-01 22:08:23
Description: An adaptive uniform linear antenna array based on LMS algorithm is simulated. The antenna array consists of four omnidirectional antennas with adjacent arrays spaced at half of the wavelength.
Plat: matlab | Size: 2551KB | Downloads: 0
SEXYLADY 2019-05-01 21:46:31
Description: Design of low-pass, band-pass and band-stop filters with Hamming window
Plat: matlab | Size: 1KB | Downloads: 1
zhuxiaonan 2019-05-01 15:37:40
Description: minxmum system of fpga based on EP2C8Q208
Plat: Verilog | Size: 25554KB | Downloads: 0
hhhaaa5 2019-04-30 21:56:08
Description: Common Verilog code, easy to write program direct call, no need to design from scratch.
Plat: WINDOWS | Size: 3850KB | Downloads: 0
名字那么费事 2019-04-30 19:06:38
Description: Sequence detection, used to detect sequences, can detect continuous sequences.
Plat: Verilog | Size: 123KB | Downloads: 0
Gopee 2019-04-30 17:09:35
Description: A carry free arithmetic operation can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). In QSD, each digit can be represented by a number from -3 to 3. Carry free addition and other operations on a large number of digits such as 64, 128, or more can be implemented with constant delay and less complexity. Design is simulated & synthesized using Modelsim6.0, Micro wind and Leonardo Spectrum.
Plat: Others | Size: 54KB | Downloads: 0
Gopee 2019-04-30 16:59:42
Description: Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Nonuniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR design approaches show that the proposed designs achieve the best area and power results.
Plat: Verilog | Size: 10KB | Downloads: 0
Gopee 2019-04-30 16:57:37
Description: This paper proposes a new single cycle access test structure for logic test. It eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles. This leads to more realistic circuit behavior during stuck-at and at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions.
Plat: Verilog | Size: 1424KB | Downloads: 0
Gopee 2019-04-30 16:54:27
Description: In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.
Plat: Verilog | Size: 5KB | Downloads: 0
Gopee 2019-04-30 16:53:25
Description: Continuous shrinking in feature size, increasing power density etc, increase the vulnerability of microprocessors against soft errors even in terrestrial applications. The register file is one of the essential architectural components where soft errors can be very mischievous because errors may rapidly spread from there throughout the whole system. Thus, register files are recognized as one of the major concerns when it comes to reliability. The paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors.
Plat: Verilog | Size: 3KB | Downloads: 0
bhautik 2019-04-30 16:46:07
Description: adc serial in parallel out
Plat: Verilog | Size: 155KB | Downloads: 0
Gopee 2019-04-30 16:26:28
Description: Although redundant addition is widely used to design parallel multi operand adders for ASIC implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on these devices (due to their specialized carry-chain resources) as well as the area overhead of the redundant adders when they are implemented on FPGAs.
Plat: Verilog | Size: 2846KB | Downloads: 0
Gopee 2019-04-30 16:15:08
Description: This work proposes the application of Advanced Encryption Standard (AES) algorithm in Universal Asynchronous Receiver Transmitter (UART) module for secure transfer of data. The proposed architecture implements AES-128 algorithm that encrypts the data before transmission through UART transmitter and decrypts after receiving the data at UART receiver module.
Plat: VHDL | Size: 16KB | Downloads: 0
mometime 2019-04-30 15:46:38
Description: JAVAEE, Product of Two Numbers
Plat: Java | Size: 7KB | Downloads: 0
csj_fpgaer 2019-04-30 13:15:54
Description: Simulated traffic lights, red, yellow and green lights turn on and off
Plat: Verilog | Size: 73KB | Downloads: 4
MassBase 2019-04-30 10:05:43
Description: ARM's official Cortex-M1 chip design code
Plat: Verilog | Size: 6223KB | Downloads: 4
wrnd 2019-04-30 02:32:21
Description: The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.
Plat: Verilog | Size: 1KB | Downloads: 6
loop_p 2019-04-29 19:05:37
Description: EDA software tanner tools v13.0 part 01
Plat: Others | Size: 4980KB | Downloads: 0
fsdrfvd 2019-04-29 19:01:30
Description: MiCAP User Guide 1 Introduction : MiCAP is a custom recon guration controller used for DCS. The repository contains the following directories:  hw: In this directory, it contains all the necessary hardware code of the MiCAP.  sw: In this directory, it contains all the necessary software drivers of the MiCAP. 2 Hardware integration: The MiCAP can be used as a pcore that can be imported in any XPS project of the DCS. The hardware source code is located at \/hw/micap v1 00 a". The user can copy this folder into
Plat: WINDOWS | Size: 141KB | Downloads: 0
fsdrfvd 2019-04-29 19:00:05
Description: MiCAP User Guide 1 Introduction : MiCAP is a custom recon guration controller used for DCS. The repository contains the following directories:  hw: In this directory, it contains all the necessary hardware code of the MiCAP.  sw: In this directory, it contains all the necessary software drivers of the MiCAP. 2 Hardware integration: The MiCAP can be used as a pcore that can be imported in any XPS project of the DCS. The hardware source code is located at \/hw/micap v1 00 a". The user can copy this folder into the user's pcores directory of the XPS project. Next, press the re-scan button in IP catalog of the XPS. The MiCAP should be visible under USER tab of the IP catalog. The user can now use as an user IP and instantiate the MiCAP core for the DCS. 3 Software integration: Once the bitstream is generated (as guided in the TLUT tool ow), copy all the les present in the directory \/sw" to the swRecon guration directory of the XPS project. The user can
Plat: WINDOWS | Size: 399KB | Downloads: 0
sunnyun 2019-04-29 17:28:35
Description: Water lamp and clock
Plat: VHDL | Size: 97KB | Downloads: 1
Terry6 2019-04-29 16:25:35
Description: FPGA itself 50M crystal oscillator, the FPGA uses IP core to divide and multiply five groups of frequencies.
Plat: Verilog | Size: 3044KB | Downloads: 0
Terry6 2019-04-29 16:19:17
Description: The breathing lamp of the FPGA gradually brightens and darkens. The 1S clock is replaced once, and the cycle is repeated.
Plat: Verilog | Size: 3130KB | Downloads: 1
12345_xl 2019-04-29 12:37:55
Description: SPI universal serial bus, 4-wire control, readable and writable operation
Plat: Verilog | Size: 1KB | Downloads: 0
皮卡丘me 2019-04-28 21:58:58
Description: 32-bit floating-point adder program and code interpretation
Plat: Verilog | Size: 1KB | Downloads: 1
18756574238 2019-04-28 14:47:03
Description: Initialization of temperature sensor
Plat: VHDL | Size: 4KB | Downloads: 0
平常心OUO 2019-04-28 11:06:32
Description: Verilog HDL Advanced Digital Design Bubble Sorting Method
Plat: Verilog | Size: 1KB | Downloads: 1
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