筱冰哥哥 2019-06-06 09:56:53
Description: Electronic stopwatch can realize the functions of pressing time, clicking pause and long press reset.
Plat: C/C++ | Size: 1KB | Downloads: 0
gccgmtvr 2019-06-05 22:32:53
Description: The Kalman filter is an "optimal recursive data processing algorithm". It is the best, most efficient and even most useful way to solve a large part of the problem. The core content of kalman filter is the five formulas that reflect its optimization estimation and recursion characteristics. Give an example to illustrate the physical meaning of the five formulas.
Plat: C/C++ | Size: 21KB | Downloads: 0
呵呵哼 2019-06-05 15:59:03
Description: Eight-digit digital transistors display different digits respectively. This scanning display mode becomes dynamic scanning and constantly changing assignment.
Plat: C/C++ | Size: 10KB | Downloads: 0
luotianyu 2019-06-05 09:33:50
Description: Implementation of Calculator Function by FPGA
Plat: VHDL | Size: 691KB | Downloads: 0
清晨1 2019-06-04 19:24:07
Description: EGO_1 nxoiaocijpwjcpoewopvkpowevko
Plat: Video | Size: 18977KB | Downloads: 0
kpbpro 2019-06-04 15:21:00
Description: ddr2 controller in vhdl
Plat: VHDL | Size: 992KB | Downloads: 0
kpbpro 2019-06-04 15:19:41
Description: ddr2 controller in verilog
Plat: Verilog | Size: 464KB | Downloads: 2
BestBoy♂ 2019-06-04 13:40:44
Description: FPGA Driver OV7670, Pure Verilog, Improve the Speed of Camera Processing
Plat: Verilog | Size: 295KB | Downloads: 0
RoJuly 2019-06-04 10:49:29
Description: Single clock CPU, has been on the board, to achieve basic R type, J, sw\lw, beq
Plat: Verilog | Size: 13308KB | Downloads: 2
octavian24 2019-06-04 01:53:35
Description: MIPS for Computer Architecture
Plat: VHDL | Size: 15KB | Downloads: 0
octavian24 2019-06-04 01:50:12
Description: labs for universitiy of Cluj Napoca
Plat: VHDL | Size: 31295KB | Downloads: 0
xiaoqianla 2019-06-04 00:20:42
Description: RTL coding style RTL Coding StylBook_Coding_Guidelines.zipe Gold
Plat: VHDL | Size: 471KB | Downloads: 0
anoo27 2019-06-03 21:29:42
Description: image processing of a coloured image based on brightness, threshold and inversion
Plat: VHDL | Size: 1662KB | Downloads: 0
anoo27 2019-06-03 21:26:29
Description: thinning process in fingerprint enhancement
Plat: VHDL | Size: 374KB | Downloads: 0
anoo27 2019-06-03 21:25:12
Description: fingerprint enhancement and authentication
Plat: VHDL | Size: 289KB | Downloads: 0
白泽彡 2019-06-03 21:13:44
Description: Using Verilog language to write program based on FPGA to control the timing of traffic lights in the Traffic module of the FPGA development board (Cyclone 3 chip) by different colors of LED lights and by using LCD1602 to display traffic lights
Plat: Verilog | Size: 2473KB | Downloads: 2
maozhedong 2019-06-03 09:40:52
Description: DDS VHDL include everything of dds AD9914
Plat: Quartus II | Size: 1129KB | Downloads: 0
dani kia 2019-06-02 23:46:02
Description: Implementation of Matrix Keyboard Using Vhdl
Plat: VHDL | Size: 3854KB | Downloads: 0
dani kia 2019-06-02 23:41:08
Description: traffic light controller using vhdl
Plat: VHDL | Size: 3923KB | Downloads: 0
dani kia 2019-06-02 23:36:12
Description: implementation of ps2 protocol on fpga using vhdl
Plat: VHDL | Size: 1901KB | Downloads: 0
dani kia 2019-06-02 23:32:09
Description: showing Keyboard characters on a Character LCD by ps2 using vhdl
Plat: VHDL | Size: 4533KB | Downloads: 0
dani kia 2019-06-02 23:24:44
Description: Creating sine wave By DAC Using FPGA
Plat: VHDL | Size: 3175KB | Downloads: 1
墨理moli 2019-06-02 16:24:44
Description: about lcd and camera
Plat: Vivado | Size: 1931KB | Downloads: 0
1999zsy 2019-06-02 10:30:54
Description: frequency divider to 500Hz
Plat: Verilog | Size: 7KB | Downloads: 1
1999zsy 2019-06-02 10:29:38
Description: frequency divider to 250Hz
Plat: Verilog | Size: 12KB | Downloads: 0
vitorz 2019-06-02 08:34:03
Description: Start project to count your project signals from the sensor
Plat: WINDOWS | Size: 130KB | Downloads: 0
HW6 2019-06-01 11:26:06
Description: 8bits Simple Frequency Meter It can test 10-10MHz square wave, 1 Hz reference clock, output the measured value in 8421BCD code form, and reset the system.
Plat: Verilog | Size: 1KB | Downloads: 0
mirtom 2019-05-31 23:25:00
Description: this is a not full wrappered code very crude use chebyshev to caculate arctan function i m urgent to download a model from pudn so i do this.
Plat: Verilog | Size: 1KB | Downloads: 0
suiyi 2019-05-31 17:50:27
Description: Thiis programm is used for ddr3 driver. if you are writing the DDR driver , it is a good reference example.
Plat: Verilog | Size: 5KB | Downloads: 2
安梦扬 2019-05-31 16:43:48
Description: AD conversion module program, simple to use, with STM32, 5V output/input....
Plat: C/C++ | Size: 31628KB | Downloads: 10
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