cissu77 2019-05-06 09:38:14
Description: led verilog led ccccccc
Plat: VHDL | Size: 1KB | Downloads: 0
港湾 2019-05-05 23:35:20
Description: This software is developed by VC ++, and has a demonstration function for the development of VC + + and electronic single chip computer.
Plat: Visual C++ | Size: 55KB | Downloads: 0
dtuzi 2019-05-05 21:17:17
Description: A fir filter design method
Plat: PDF | Size: 116KB | Downloads: 0
eng_hala 2019-05-05 18:54:57
Description: FPGA implementation for adder
Plat: Verilog | Size: 8833KB | Downloads: 0
zwq12311 2019-05-05 18:52:50
Description: PCB board subroutine, AD open, can directly corrode without wiring
Plat: Verilog | Size: 3438KB | Downloads: 0
eng_hala 2019-05-05 18:51:01
Description: implementation for ALU with ripple carry adder
Plat: Verilog | Size: 6897KB | Downloads: 0
zhaolinlin 2019-05-05 16:27:36
Description: The USB source code and USB-related information can help USB beginners to learn USB protocol and programming better.
Plat: Verilog | Size: 4744KB | Downloads: 0
山姜 2019-05-05 15:57:08
Description: BPSK is modulated by vhdl, with 0 and 180 degree phase and two output channels
Plat: VHDL | Size: 521KB | Downloads: 0
开心狗狗 2019-05-05 15:46:44
Description: Arithmetic Logic Operator, which has two functions, chooses function modules through control signals
Plat: VHDL | Size: 467KB | Downloads: 1
小清松 2019-05-05 13:54:16
Description: Serial debugging assistant sends the number of hexadecimal 1-16 to the FPGA, which is shown by the lamp. The baud rate can be set.
Plat: Verilog | Size: 441KB | Downloads: 1
godxun 2019-05-05 10:31:33
Description: Program for sending data from computer and receiving data by FPGA, UART module
Plat: Verilog | Size: 17969KB | Downloads: 1
吴彦祖家里 2019-05-05 10:04:05
Description: SPI program has been applied and verified in practice
Plat: Verilog | Size: 4KB | Downloads: 3
steven54321 2019-05-05 09:01:36
Description: Design of 16-bit synchronous adder and multiplier Requirements: (1) Analysis of 16-bit synchronous adder and multiplier structure and circuit characteristics; (2) Design with hardware description language; (3) Writing test simulation and simulation. Design a simple frequency meter with 8 digit display. Requirement: It can test 10 Hz ~ 10 MHz square wave signal. (2) The reference clock input by the circuit is 1Hz, which requires the measured value to be output in the form of 8421BCD code. (3) The system has reset keys; (4) The design is based on Verilog HDL with the method of hierarchical module.
Plat: Verilog | Size: 20KB | Downloads: 1
Kevaen 2019-05-05 00:53:56
Description: rgb to YCbCr converter
Plat: Vivado | Size: 4719KB | Downloads: 0
ninpo 2019-05-04 16:22:29
Description: Multipelexer Verilog code
Plat: Verilog | Size: 2KB | Downloads: 0
陈惜 2019-05-04 16:14:06
Description: Solutions for computer experiment.
Plat: Others | Size: 33992KB | Downloads: 1
陈惜 2019-05-04 16:11:17
Description: Computer composition and system design
Plat: Others | Size: 12633KB | Downloads: 1
陈惜 2019-05-04 16:07:18
Description: Verilog instruction book
Plat: Others | Size: 6931KB | Downloads: 1
frostmorne 2019-05-04 15:30:19
Description: Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code
Plat: Verilog | Size: 7KB | Downloads: 6
Uthou 2019-05-03 23:19:44
Description: Various functions of Verilog are realized, and the clock frequency is easy to adjust.
Plat: Verilog | Size: 355KB | Downloads: 0
youqi 2019-05-03 13:31:27
Description: The system Verilog verification platform of the Peace Dispute Machine module, including the modelsim/questasim project file, is compiled and can be used directly.
Plat: Verilog | Size: 248KB | Downloads: 1
J.K 2019-05-03 11:07:04
Description: FIR, VHDL CODE and simulation data
Plat: VHDL | Size: 27KB | Downloads: 2
Pakki1 2019-05-03 01:06:13
Description: All digital phase locked loop project
Plat: VHDL | Size: 30150KB | Downloads: 1
羊羊驼 2019-05-02 23:24:41
Description: Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence. The elements of the sequence are the 10 Numbers [0-9], each of which corresponds to a 4-bit binary representation. Let's say 5 is equal to 0101, and 9 is equal to 1001. The length of the input data sequence is 256. First output the encoding of each element, and then output the data sequence corresponding Huffman coding sequence. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient (4) write the test simulation program.
Plat: VHDL | Size: 178KB | Downloads: 12
羊羊驼 2019-05-02 23:23:34
Description: Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient (4) write the test simulation program.
Plat: VHDL | Size: 334KB | Downloads: 11
羊羊驼 2019-05-02 23:21:54
Description: The barker code correlator can detect the barker code sequence peak, and can detect the barker code sequence peak in the case of 1bits error. Barker code is a binary code group with special rules proposed by r.h. barker in the early 1950s. It is an aperiodic sequence, an n-bit barker code (x1, x3... Xn), each symbol can only value +1 or -1. And the barker code for eleven is 11 'b11100010010.
Plat: VHDL | Size: 365KB | Downloads: 4
羊羊驼 2019-05-02 23:20:25
Description: Design a simple frequency meter with 8-digit display. Requirements: (1) able to test 10Hz~10MHz square wave signal; The circuit input reference clock is 1Hz, the measurement value in 8421BCD code output; The system has reset key; (4) using the method of hierarchical module, Verilog HDL design. Write the test simulation program
Plat: VHDL | Size: 2964KB | Downloads: 7
彩云之南7 2019-05-02 21:09:36
Description: Comprehensive training platform operation instruction and extended module experiment instruction
Plat: Verilog | Size: 4761KB | Downloads: 0
@低熵体 2019-05-02 21:04:04
Description: Music Player Based on VHDL/FPGA/verilog
Plat: VHDL | Size: 68KB | Downloads: 0
asod99 2019-05-02 18:31:27
Description: aopdp opowdo pawopd kpoawd
Plat: digsilent | Size: 6KB | Downloads: 0