郭静 2011-03-08 17:49:41
Description: CORDIC algorithm requires: CORDIC algorithm code, written in a module, there are input and output, principles, procedures, results, a simulation waveform
Plat: VHDL | Size: 69KB | Downloads: 56
陈华 2011-01-24 17:42:24
Description: CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, including trigonometric, square root, exponential, logarithmic, square root and other functions.
Plat: VHDL | Size: 1KB | Downloads: 145
Jean-Louis 2011-01-24 06:09:01
Description: Programs I wrote for 8051 processors, including : - Various multiplications (16x16, 32x8...) - div, atn, ln, sin, sqrt - bresenham for line and circle - 32bit cordic (linear, circular, hyperbolic) - date conversion - random generation - RS232 drivers - LCD (2x16) driver - etc. (squelett.a51 is an exemple of main programm)
Plat: Asm | Size: 78KB | Downloads: 7
rams 2011-01-22 11:49:10
Description: cordic for generating sine wave
Plat: TEXT | Size: 2KB | Downloads: 6
rams 2011-01-22 11:48:04
Description: cordic algorithm using verilog code
Plat: TEXT | Size: 1KB | Downloads: 3
nnmb 2011-01-16 02:00:10
Description: CORDIC arctangent(atan) Simulink model. You can generate HDL from this model
Plat: matlab | Size: 30KB | Downloads: 32
千年一叹 2011-01-14 11:02:51
Description: failed to translate
Plat: VHDL | Size: 2KB | Downloads: 32
baba12345 2011-01-11 20:56:21
Description: CORDIC algorithm based on high-speed processor design based _4FFT
Plat: Others | Size: 439KB | Downloads: 3
surekha 2011-01-03 18:12:30
Description: it describes the cordic program for trigonometric function
Plat: VHDL | Size: 237KB | Downloads: 2
hlayumi 2011-01-01 21:52:46
Description: cordic the verilog design, qII implementation, relatively simple complaints about the implementation process of the algorithm.
Plat: VHDL | Size: 1690KB | Downloads: 23
daisywmc 2010-12-30 19:53:58
Description: By converting complex arithmetic into simple operations such as adding and shift then gradually approach the exact result, CORDIC algorithm keeps balance between precision, speed and hardware complexity, and whose combination with VLSI performs a great role in the hardware implementation of DSP algorithm, enhance CORDIC has been widely used in the field of digital signal processing. We studied the principle of CORDIC algorithm, and described the pre and post process of dual mode CORDIC algorithm, then the pipelined dual-mode CORDIC algorithm is implemented based on FPGA.
Plat: VHDL | Size: 385KB | Downloads: 39
daisywmc 2010-12-30 19:49:09
Description: Abstract: In this paper, based on the traditional CORDIC algorithm, by increasing the number of iterations, selection of parameters were optimized to improve the computing precision, the design of the soft-core to the occasion in the high precision in the running, such as real-time voice , image signal processing, filtering technology. IEEE-754 output data after standardization, can be directly compatible with most processors, expanded its scope of application. Altera, Nios Ⅱ ultimately by the processor the way to add custom instructions to complete the hardware. Keywords: CORDIC, custom instruction, IEEE-754 standard treatment.
Plat: VHDL | Size: 223KB | Downloads: 13
zp 2010-12-10 21:22:06
Description: cordic algorithm analysis and implementation, analysis is pretty good
Plat: VHDL | Size: 2073KB | Downloads: 33
脡ricles R. Sousa 2010-12-01 03:47:13
Description: Paper about the CORDIC.
Plat: VHDL | Size: 278KB | Downloads: 8
huuhung 2010-11-29 11:10:50
Description: - CORDIC for sine cosine computation
Plat: VHDL | Size: 281KB | Downloads: 13
soussou 2010-11-29 06:29:56
Description: the cordic algorithm on matlab
Plat: matlab | Size: 131KB | Downloads: 36
youir 2010-11-25 01:57:38
Description: describtif of cordic algo
Plat: PDF | Size: 174KB | Downloads: 3
LILI 2010-11-21 07:10:22
Description: CORDIC implementation procedures for this section, reference to paper to accelerate the realization of CORDIC Algorithm
Plat: C/C++ | Size: 1KB | Downloads: 8
hlayumi 2010-11-17 20:24:36
Description: In QUARTUS environment, through the Verilog implementation cordic, generate sin, cos
Plat: VHDL | Size: 1669KB | Downloads: 192
任静 2010-11-04 03:31:17
Description: CORDIC algorithm VHDL FPGA
Plat: VHDL | Size: 1KB | Downloads: 10
对的1111 2010-11-03 11:09:17
Description: cordic algorithm
Plat: matlab | Size: 384KB | Downloads: 48
xyz002 2010-10-15 19:10:09
Description: atan function using cordic
Plat: Windows_Unix | Size: 1KB | Downloads: 15
朱子翰 2010-10-09 18:32:09
Description: Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
Plat: VHDL | Size: 1KB | Downloads: 83
朱子翰 2010-10-09 18:31:05
Description: Written by matlab cordic phase of the program for the extraction phase and amplitude
Plat: matlab | Size: 2KB | Downloads: 59
Fengxiaodong 2010-09-26 12:26:12
Description: Algorithm to achieve cordic with verilog. Multi-mode, there vecter and rotate mode. Support for multiple output
Plat: VHDL | Size: 353KB | Downloads: 12
champ 2010-09-15 14:47:39
Description: cordic algorithm of the core code, written by foreigners. I have verified, is not fully used! Please rest assured to download.
Plat: VHDL | Size: 278KB | Downloads: 180
vonsquidy 2010-09-09 09:34:02
Description: This is a vhdl synthesis of the CORDIC method.
Plat: VHDL | Size: 120KB | Downloads: 7
李山 2010-08-14 21:37:13
Description: The structure of cordic iterative algorithm based on verilog writing code, hardware
Plat: VHDL | Size: 2KB | Downloads: 10
Nagendran 2010-07-25 16:43:50
Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be different from the standard FFT algorithm. This variation in gain is not important for orthogonal frequency division modulation (OFDM) and demodulation. The gain can be corrected, to that of a conventional FFT, by applying a constant multiplying factor.
Plat: VHDL | Size: 179KB | Downloads: 73