赵联开 2017-11-17 13:34:38
Description: Timing diagrams of two EC11 rotary encoders captured by logic analyzer for certain bits to one pulse or two to one pulse. It includes forward rotation, reverse rotation, continuous forward rotation, and successive inversion sequence.
Plat: WINDOWS | Size: 318KB | Downloads: 0
王守伟 2017-11-17 10:18:13
Description: Provision of modular multiplication using Montgomerie algorithm
Plat: C-C++ | Size: 385KB | Downloads: 0
XH 2017-11-15 17:17:22
Description: soinmgvoi mwpgevp epoikasobiej peiwamp kmrepogp keap[g epag[tp ijatoihbwho aogjao jsaogj josgv jowgjo b jwoj jowsjw; wsjg;owi n
Plat: C51 | Size: 104KB | Downloads: 1
炽热的心 2017-11-15 10:02:21
Description: SIM card common deck package comes from the excerpt
Plat: WINDOWS | Size: 37KB | Downloads: 1
陈少杰 2017-11-13 20:48:38
Description: 0 to 59 minutes and 59 seconds of motion timer with reset pause button start function
Plat: Quartus II | Size: 522KB | Downloads: 0
王帅 2017-11-05 16:34:57
Description: Dual motor drive schematic diagram and PCB wiring diagram, two motors separately control, can achieve positive and reverse motor, motor speed control of PWM.
Plat: Altium | Size: 38852KB | Downloads: 2
yuhai 2017-11-05 09:33:13
Description: Circuit diagram of driving LCD screen designed by STM32F105 and FPGA
Plat: Cadence skill | Size: 228KB | Downloads: 0
yuhai 2017-11-05 09:26:22
Description: The schematic diagram of the lock control panel of the express cabinet is designed by using ALTIUM DESIGNER
Plat: WINDOWS | Size: 868KB | Downloads: 1
xx 2017-11-04 14:27:46
Description: instruction for mtdutils
Plat: LINUX | Size: 20KB | Downloads: 0
xx 2017-11-04 14:21:27
Description: mtd-utils is a tool for operate flash in linux
Plat: LINUX | Size: 836KB | Downloads: 0
蔡鹏飞 2017-11-03 15:29:15
Description: the interduce of 53L0 API
Plat: C-C++ | Size: 710KB | Downloads: 1
chenqingwei 2017-11-02 13:00:21
Description: The working principle of switch power supply for single FireWire is discussed in detail The power supply of the single wire switch is generally divided into two parts to realize the power supply of the control circuit: off state power supply and open supply Electricity, the following are explained
Plat: C-C++ | Size: 1972KB | Downloads: 0
程威 2017-11-02 08:18:33
Description: Display drive P10 monochrome LED screen
Plat: C-C++ | Size: 3469KB | Downloads: 3
黄熙 2017-11-01 12:07:08
Description: Document includes nebulizer source, schematic diagram, circuit diagram
Plat: C-C++ | Size: 19660KB | Downloads: 2
寇经纬 2017-11-01 11:13:52
Description: example code,make your hardware design more simple
Plat: Verilog | Size: 1535KB | Downloads: 0
寇经纬 2017-11-01 11:09:48
Description: example code...make it easy to develop hardware
Plat: Verilog | Size: 1567KB | Downloads: 0
captain 2017-10-31 14:15:06
Description: .DSN schematic diagram of dm8127
Plat: WINDOWS | Size: 380KB | Downloads: 0
Peng 2017-10-31 03:35:30
Description: nuc970 demo sch sc .sn
Plat: WINDOWS | Size: 281KB | Downloads: 0
Peng 2017-10-31 03:05:12
Description: iMX28_EVK_DesignFiles
Plat: WINDOWS | Size: 7441KB | Downloads: 0
Jiri Hruska 2017-10-26 03:22:18
Description: Manuals for Sebury access system (RFID readers, keypads, access systems)
Plat: PDF | Size: 17808KB | Downloads: 0
期望 2017-10-25 22:04:04
Description: ZRTECH core board procedures and PDF instructions, complete project, it is worth collecting
Plat: Verilog | Size: 6051KB | Downloads: 1
崔丹丹 2017-10-23 10:46:46
Description: PLL, pll. It's an important resource in FPGA. Because a complex FPGA system often requires multiple clock signals with different frequencies and phases. Therefore, the number of PLL in a FPGA chip is an important indicator of the ability of FPGA chip. In the design of FPGA, the high speed design of clock system FPGA is extremely important. A low jitter and low delay system clock will increase the success rate of FPGA design. This routine calls the PLL core provided by Xilinx to generate clocks of different frequencies, and outputs one of the clocks to the external IO of the FPGA, that is, the SMA interface of the development board.
Plat: VHDL | Size: 216KB | Downloads: 0
李鹏飞 2017-10-19 11:14:51
Description: Simple hardware description Language Verilog language described 128 binary counter.
Plat: Verilog | Size: 1KB | Downloads: 0
李欣 2017-10-16 09:47:31
Description: This is a digital potentiometer X9C104 document, the chip produced by INTERSIL company, 3-wire serial interface, 99 resistor units, 5V power supply.
Plat: MDK | Size: 225KB | Downloads: 2
张天才 2017-10-13 15:15:16
Description: SystemVerilog user Guide
Plat: Verilog | Size: 5463KB | Downloads: 1
tony 2017-10-10 17:48:21
Description: The brake controller, using PWM to control the motor brake, brake in effective opening off brake fever
Plat: MDK | Size: 1193KB | Downloads: 1
LTH 2017-10-09 12:12:39
Description: Microcontroller, capacitor, touch screen, hardware, PCB design, layout
Plat: WINDOWS | Size: 439KB | Downloads: 0
LTH 2017-10-09 12:04:57
Description: Altera SOC H264 codec demonstration program
Plat: Verilog | Size: 52496KB | Downloads: 4
韩旭 2017-09-26 10:24:16
Description: Calculate the look-up table and the B value of the thermistor
Plat: Java | Size: 8KB | Downloads: 0
王逸朔 2017-09-20 18:43:18
Description: Msp430f6638 learning routines, including LED, LCD, buttons, ADC, DAC various modules
Plat: C-C++ | Size: 22412KB | Downloads: 1
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