王逸朔 2017-09-20 18:43:18
Description: Msp430f6638 learning routines, including LED, LCD, buttons, ADC, DAC various modules
Plat: C-C++ | Size: 22412KB | Downloads: 0
桑亚雷 2017-09-20 09:14:07
Description: LCL inverter capacitor current feedback and inverter side current feedback active damping
Plat: matlab | Size: 80KB | Downloads: 0
史嘉琦 2017-09-06 14:39:11
Description: 16 bit mode conversion chip MCP3424 header file
Plat: C-C++ | Size: 5KB | Downloads: 1
史嘉琦 2017-09-06 14:36:27
Description: Digital potentiometer AD5242 header file for circuit development calls
Plat: C-C++ | Size: 4KB | Downloads: 0
熊猫松松 2017-09-04 23:53:01
Description: several adder designed by Verilog
Plat: Verilog | Size: 1KB | Downloads: 0
杨雷 2017-09-03 17:28:40
Description: LCD module specification for approval
Plat: C-C++ | Size: 18KB | Downloads: 0
刘永 2017-09-02 18:29:22
Description: PIC18F2550 USB HID Demo
Plat: C++ | Size: 329KB | Downloads: 0
pankaj patel 2017-08-31 15:06:29
Description: 16 IO with cpu and addon card schematic
Plat: PLC | Size: 167KB | Downloads: 0
pankaj patel 2017-08-31 15:02:47
Description: PLC Schematic for reference of new design
Plat: PLC | Size: 19KB | Downloads: 1
huhongyang 2017-08-28 18:27:35
Description: Streamlined verilong serial communication source code, with communication custom module
Plat: WINDOWS | Size: 16KB | Downloads: 0
杨政军 2017-08-25 09:31:14
Description: 120 degree trapezoidal wave drive motor
Plat: C-C++ | Size: 5KB | Downloads: 2
2017-08-25 08:57:35
Description: This is a tilt sensor testing procedures, the use of C programming language.
Plat: Delphi | Size: 40KB | Downloads: 0
桑亚雷 2017-08-18 22:28:03
Description: An active power filter (APF) that using PI+ repetitive control
Plat: matlab | Size: 63KB | Downloads: 8
qen 2017-08-18 14:42:49
Description: Die taking method PCtoLCD2002.exe
Plat: MDK | Size: 3257KB | Downloads: 1
张泽宾 2017-08-18 10:30:45
Description: Using Verilog language to implement SPI transport protocol
Plat: VHDL | Size: 4KB | Downloads: 1
xjj 2017-08-15 12:46:16
Description: Application of CS5460 chip in MSP430 single chip microcomputer
Plat: C-C++ | Size: 50KB | Downloads: 0
张乐 2017-08-14 00:00:27
Description: Matrix keyboard, row and column scanning
Plat: C-C++ | Size: 1KB | Downloads: 0
支岚 2017-08-08 08:45:53
Description: 74LS138 and 74ls48 use 8 bit digital tube static display
Plat: MultiPlatform | Size: 197KB | Downloads: 0
张炯 2017-08-03 16:24:30
Description: Correction formula of three dimensional electronic compass based on single chip microcomputer
Plat: Others | Size: 2131KB | Downloads: 0
赖鹏 2017-07-20 23:55:43
Description: Electronic Perpetual Calendar
Plat: Visual C++ | Size: 65KB | Downloads: 0
张警官 2017-07-19 14:47:08
Description: Motor driven closed loop control
Plat: WINDOWS | Size: 2303KB | Downloads: 3
石原 2017-07-17 15:24:52
Description: A4988 stepper motor driver
Plat: WINDOWS | Size: 31234KB | Downloads: 7
freddy 2017-07-17 10:17:00
Description: Wind control pendulum system
Plat: C-C++ | Size: 639KB | Downloads: 1
kaison 2017-07-14 14:43:21
Description: Capacitive touch switch based on STC single chip microcomputer hardware design
Plat: WINDOWS | Size: 205KB | Downloads: 1
陈超 2017-07-11 10:05:28
Description: realize the function of waterfall light based on FPGA.
Plat: Verilog | Size: 3055KB | Downloads: 0
闫溪芮 2017-07-10 16:10:53
Description: This is a design for the msp430f5529 and AY-SEB development boards. The output is controlled by pressing the key and the output is displayed on the LCD screen
Plat: C-C++ | Size: 3KB | Downloads: 0
马乾峰 2017-07-10 10:17:19
Description: Measurement of temperature and humidity with DHT11 sensor based on STM32F10X series
Plat: C-C++ | Size: 3796KB | Downloads: 0
farrokh.razavi.1363 2017-07-09 03:36:48
Description: Compiling module mult11sx8s Compiling module dwt_1 Compiling module top_dwt Compiling module glbl Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish...
Plat: VHDL | Size: 2KB | Downloads: 0
farrokh.razavi.1363 2017-07-09 03:35:56
Description: Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse CPU Usage: 1435 ms
Plat: VHDL | Size: 2KB | Downloads: 0
慕南枝 2017-07-08 17:40:30
Description: This is the code of two-roll balanced car.
Plat: Visual C++ | Size: 4514KB | Downloads: 1
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