q7895123q 2020-09-25 20:20:43
Description: DE10-Lite_User_Manual.pdf
Plat: VHDL | Size: 4829KB | Downloads: 0
"微笑的海风、 2020-09-25 19:09:30
Description: According to the structure of can chip saj1000 controller, the CAN controller is written
Plat: VHDL | Size: 860KB | Downloads: 0
CasterLiu 2020-09-25 17:27:53
Description: Bupt computer composition principle final project, hardwired controller, decompression after all into the quartus can be
Plat: VHDL | Size: 160KB | Downloads: 0
·封个 2020-09-24 17:45:51
Plat: Verilog | Size: 2813KB | Downloads: 0
·封个 2020-09-24 17:44:10
Plat: Verilog | Size: 1863KB | Downloads: 0
·封个 2020-09-24 17:42:02
Description: ALINX board teaching forRAM base on FPGA
Plat: Verilog | Size: 5464KB | Downloads: 0
·封个 2020-09-24 17:40:12
Plat: Verilog | Size: 45KB | Downloads: 0
小洛123 2020-09-24 10:33:34
Description: AD9854 VHDL, can be used directly, test completed very good use;
Plat: VHDL | Size: 1KB | Downloads: 0
收到订单单独 2020-09-24 10:20:44
Description: digital signal processing
Plat: Verilog | Size: 833KB | Downloads: 0
王小鸭 2020-09-23 13:43:59
Description: Implementation of single cycle CPU
Plat: VHDL | Size: 133KB | Downloads: 0
cyh1991 2020-09-23 09:25:42
Description: Implementation of UDP TCP routine in w5500
Plat: Verilog | Size: 1369KB | Downloads: 0
aminyyt 2020-09-22 21:09:24
Description: xapp861 doc for xillinx co application note
Plat: VHDL | Size: 57KB | Downloads: 0
richman 2020-09-22 16:51:06
Description: Mini 8051 Core Verilog RTL Code
Plat: Verilog | Size: 2541KB | Downloads: 0
ijsanher 2020-09-22 09:55:36
Description: test purposes only new document 2
Plat: Perl | Size: 24KB | Downloads: 0
1637米深蓝 2020-09-18 14:36:45
Description: Verilog FPGA development of key dithering routine
Plat: Verilog | Size: 3305KB | Downloads: 1
yuancwei 2020-09-18 11:42:58
Description: The periodic pulse signal is generated. The unit of pulse period can be matched, and the pulse period can be matched.
Plat: Verilog | Size: 1KB | Downloads: 0
yuancwei 2020-09-18 11:39:14
Description: The input pulse can be expanded and the width can be configured. It contains two modules.
Plat: Verilog | Size: 1KB | Downloads: 0
yuancwei 2020-09-18 11:24:53
Description: Asynchronous FIFO, read and write with different clocks. Implemented with LUT.
Plat: Verilog | Size: 2KB | Downloads: 0
山粉小圆子 2020-09-18 09:04:20
Description: Sampling ad9481 with FPGA
Plat: Verilog | Size: 32KB | Downloads: 1
wulfvood1234 2020-09-18 01:58:47
Description: Samples how work with display LCD1602 on board A-C4E6E10
Plat: VHDL | Size: 3412KB | Downloads: 0
大树0429 2020-09-17 18:05:58
Description: When the digital clock is 1 Hz, it returns to zero at 23:59:59; The crystal oscillator is 50MHz; Chip: ep4ce6e22c8n
Plat: Verilog | Size: 3387KB | Downloads: 0
Mike754 2020-09-17 17:16:50
Description: UVM with description on the how to monitor system
Plat: Verilog | Size: 110KB | Downloads: 0
阔阔栗 2020-09-16 23:34:30
Description: The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.
Plat: Verilog | Size: 2407KB | Downloads: 0
阔阔栗 2020-09-16 23:33:28
Description: 1. Use quartus to generate. MIF file, and then import sine wave data 2. Use LPM function to customize a ROM with 8 bit data width and 128 byte depth; use MATLAB and FPGA to realize the sine wave generator based on ROM
Plat: Verilog | Size: 2343KB | Downloads: 0
阔阔栗 2020-09-16 23:31:56
Description: The phase accumulator is composed of adder and register. The adder completes the addition, and the register saves the result of the adder to prepare for accumulation. It goes round and round until the accumulator overflows. Verilog HDL is used to combine the adder and the register.
Plat: Quartus II | Size: 1443KB | Downloads: 0
阔阔栗 2020-09-16 23:29:16
Description: Frequency divider is a basic component with very high frequency in FPGA design. The clock divider designed by ourselves can achieve the purpose of clock operation with only a few logic units. This code realizes the function of frequency division on FPGA.
Plat: Verilog | Size: 1400KB | Downloads: 0
阔阔栗 2020-09-16 23:27:04
Description: The counter is composed of a basic counting unit and some control gates, while the counting unit is composed of a series of triggers with the function of storing information. These triggers include RS trigger, t trigger, D trigger and JK Trigger. This code realizes the function of accumulator in FPGA
Plat: Verilog | Size: 1412KB | Downloads: 0
lys0825 2020-09-16 18:30:37
Description: The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform
Plat: Others | Size: 10278KB | Downloads: 1
张伟2223 2020-09-16 15:06:19
Description: DDS direct frequency generation of engineering code source file
Plat: Verilog | Size: 11143KB | Downloads: 1
panshi221 2020-09-16 06:38:46
Description: This book reveals the design art of hardware architecture, covering the author's experience and research results in chip design industry for more than ten years. This book is divided into nine chapters. Chapter 1 introduces the concept of metastable state, quantization methods and techniques to reduce its influence; Chapter 2 introduces clock technology of synchronous design, and puts forward feasible clock scheme and system reset strategy. Chapter 3 introduces the problems and solutions when using asynchronous clock or "processing multiple clocks" in design. Chapter 4 introduces all aspects and implementation methods of clock divider. Chapter 5 describes low power design techniques to reduce dynamic and static power consumption.
Plat: Verilog | Size: 29794KB | Downloads: 0