SakuraForever 2018-04-26 15:28:43
Description: Through the realization of pure HDL logic, image acquisition, storage and processing of ov7725 camera, including median filtering, edge detection and other classic image algorithms.
Plat: Verilog | Size: 910KB | Downloads: 0
albertyl 2018-04-26 15:27:20
Description: Use STM32 to complete the FFT transformation of the recorded music using the DSP library.
Plat: C-C++ | Size: 4830KB | Downloads: 0
坏小伙 2018-04-26 13:29:30
Description: MSK demodulation FPGA code based on Verilog, modsim simulation is correct
Plat: Verilog | Size: 7425KB | Downloads: 0
坏小伙 2018-04-26 13:25:28
Description: Verilog based MSK modulation program written, modsim simulation waveform correct
Plat: Verilog | Size: 1059KB | Downloads: 0
坏小伙 2018-04-26 13:19:42
Description: 2FSK modulation program based on Verilog, Simulink simulation passed
Plat: Verilog | Size: 951KB | Downloads: 0
罗君 2018-04-26 10:22:36
Description: By collecting input information, the program compares with the storage value of FPGA. If the password is correct, the unlocked circuit opens; if the password is wrong, the lock is not open, and the counter performs the +1 operation; the cumulative 3 time input password error gives the alarm a high level and allows the alarm to be sent to the alarm.
Plat: Quartus II | Size: 15760KB | Downloads: 0
fsmaidou 2018-04-26 09:51:05
Description: i2c bus,base on FPGA, and verification at the platform,it is right
Plat: Verilog | Size: 6KB | Downloads: 1
Dream0 2018-04-26 09:47:51
Description: UART serial communication protocol and controller design under FPGA
Plat: Verilog | Size: 1KB | Downloads: 0
hnxldx 2018-04-26 09:45:52
Description: Green online cracking WORD encryption function, after repeated use of normal function available.
Plat: ASP | Size: 3494KB | Downloads: 0
pt呀呀呀 2018-04-26 00:39:01
Description: SRAM of the AHB interface for reading and writing tests
Plat: Verilog | Size: 281KB | Downloads: 5
zbw 2018-04-25 16:33:30
Description: Multi cycle Verilog design, 5 level pipeline, CPU.
Plat: Verilog | Size: 6KB | Downloads: 0
zbw 2018-04-25 16:31:44
Description: Verilog module design and test of vending machine, simple state machine.
Plat: Verilog | Size: 12KB | Downloads: 0
zbw 2018-04-25 16:24:59
Description: The module of data cache is designed to connect the pipeline MEM module.
Plat: Verilog | Size: 2KB | Downloads: 0
zbw 2018-04-25 16:21:32
Description: Implementation of a five level pipelining structure for a simple ori instruction
Plat: Verilog | Size: 375KB | Downloads: 0
三棵树机务段 2018-04-25 15:00:11
Description: 135 classic examples of Verilog design
Plat: Verilog | Size: 164KB | Downloads: 0
New2018 2018-04-24 15:36:59
Description: The sequence detector of 110 adds the enable end to check its correctness.
Plat: Verilog | Size: 187KB | Downloads: 0
GMKR 2018-04-24 13:59:07
Description: booth multiplier using booth algorithm
Plat: Verilog | Size: 11KB | Downloads: 0
小吧ui 2018-04-24 12:36:28
Description: High precision square wave frequency meter
Plat: VHDL | Size: 1KB | Downloads: 0
青龙山梁朝伟 2018-04-22 22:37:33
Description: Verilog code for 128 bit AES cipher based on PPRM3S box
Plat: Verilog | Size: 15KB | Downloads: 0
光暗相间 2018-04-22 21:38:28
Description: produce pseudo-random code,and then get it into AMI code
Plat: Quartus II | Size: 126KB | Downloads: 0
xhl81 2018-04-22 16:15:43
Description: EFEDBFBTNGHNFNBRBBFDNHGNFB
Plat: Python | Size: 6KB | Downloads: 0
yymj 2018-04-22 14:53:04
Description: drive CCD 1705 from Toshiba
Plat: Quartus II | Size: 462KB | Downloads: 0
skyrocket 2018-04-22 14:37:53
Description: Familiar with the basic SOPC development process, and quickly grasp the SOPC development.
Plat: Verilog | Size: 1991KB | Downloads: 0
wsf-jv 2018-04-22 13:22:09
Description: FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design example posted on the Altera Support website: http://www.altera.com/support/examples/exm-index.html Ensure that you have read the information on the design example web page before using the example. This readme file contains the following sections: o Package Contents o Tool Requirements o Quartus II Compilation o ModelSim Simulation Models o MATLAB Models o Core Directory Names o Release History o Design Examples Disclaimer o Contacting Altera
Plat: Verilog | Size: 1094KB | Downloads: 0
wsf-jv 2018-04-22 13:14:56
Description: FPGA implementation of various cryptographic algorithms
Plat: VHDL | Size: 17491KB | Downloads: 0
wsf-jv 2018-04-22 13:10:26
Description: Implementation of FFT on FPGA 1. the implementation of 1024 point FFT algorithm based on FPGA; 2. the design and implementation of FFT algorithm based on FPGA; 3. design and implementation of a variable point FFT processor based on FPGA.
Plat: Verilog | Size: 18444KB | Downloads: 2
田联合 2018-04-22 04:02:36
Description: usart Ustartled control code for test use, P10 unit available
Plat: C-C++ | Size: 4KB | Downloads: 0
硅渣渣 2018-04-21 21:57:15
Description: After power up, our design will send a given data code, then the receiving module will accept the data that it sends and display it on the digital tube. Then we can use our remote control keyboard to send the data, the receiving module is received and displayed.
Plat: Verilog | Size: 426KB | Downloads: 2
硅渣渣 2018-04-21 21:49:42
Description: By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.
Plat: Verilog | Size: 348KB | Downloads: 0
硅渣渣 2018-04-21 21:45:56
Description: The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input, byte 1024, signal all set to low level and so on. Our module drive clock is configured as an internal output clock, that is, let FX2 give our design as the clock source, and output a clock with the largest configuration clock 48M.
Plat: Verilog | Size: 420KB | Downloads: 0
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