Description: GTP module is mainly divided into the main function module described in Chinese

Description: 24 counter, and digital display

Description: Power System Transient Stability Program, can be transient stability, Rapid expansion of random spanning tree algorithm, FMCW frequency modulated continuous wave radar range and angular measurements.

Description: sdram control module

Description: 1Hz clock signals commonly used in engineering, the use of VHDL language to write

Description: 10 seconds counter module VHDL source code, in FPGA realize counter function

Description: decode_1553b_model.v

Description: Optimization class contains several simple sample programs, MIMO OFDM matlab simulation, Includes the modulation, demodulation, signal to noise ratio calculation.

Description: LED light principle is, according to the LED hardware circuit connection to the corresponding port, high or low level can light.

Description: By setting the clock to achieve pulse width modulation of the Verilog code and test

Description: moore logic realization

Description: 1602 program, apply to FPGA/VHDL for LCD1602 LCD screen control.

Description: It describes the application of load forecasting, Chaos indicator for Lyapunov index calculation, Ensure accurate communication is learning a good helper.

Description: This is a Altera based FPGA digital display software, has been debugging through.

Description: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.

Description: Many Verilog language programs can implement many functions. There are detailed routines and explanations PDF.

Description: In the STM32 board and computer serial assistant for communication, using the serial port DMA way, first receive, and then sent to the PC terminal, you can receive continuously, sent through the button once

Description: reduced basis for schrodnger

Description: FPGA 8 bit SPI information transfer as a cluster machine......

Description: VGA asdfghjkkkkkkkkkkkkkkk

Description: This code completes the design of pipelined CPU

Description: what are you doing for your life. You are so young, you have pashion and what the hell are you doing right now

Description: wuxiantongxinFPGA VERILOG HDL

Description: UART function module, Verilog, simple and practical

Description: The simulation voltage output is controlled by spi reading and writing 16 digits

Description: (1) the spike sequence of Barker code can be detected; (2) the spike sequence of Barker code can be detected under the condition of 1bits error

Description: Spi communication for fpga

Description: The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words.

Description: Tlk1221 chip information, mainly tlk1221 chip circuit applications.

Description: Simple bus stop program, the use of Verilog HDL language