wangshouli414 2019-03-23 09:30:38
Description: uart module,including tx and rx module.
Plat: Verilog | Size: 1KB | Downloads: 0
JUNGLE2018 2019-03-23 01:17:08
Description: DDS signal generator can produce sinusoidal signal. Sawtooth wave, trapezoidal wave
Plat: Verilog | Size: 3342KB | Downloads: 0
RockyMa 2019-03-22 23:34:53
Description: 1. Using Verilog HDL language to design a simple two-way intersection traffic light control system. 2. Description: The main function of the control system is to control the status of red and green lights and show the duration of the current status. A traffic control system designed here has three states: emergency state, test state and normal working state. Emergency state is used to deal with some sudden states, such as martial law, when two-way intersection is prohibited; test state can be used to detect whether the hardware of signal lights and digital tubes is normal; normal working state is used to control the signal lights of two-way intersection.
Plat: Verilog | Size: 9452KB | Downloads: 0
RockyMa 2019-03-22 23:28:15
Description: 1. Design of an eight-bit full adder by using a one-and-a-half adder 2. Functional simulation
Plat: Verilog | Size: 678KB | Downloads: 0
RockyMa 2019-03-22 23:21:55
Description: 1. Referring to parity check/generation module and 4-bit parallel serial shift register module, UART serial transmission/receiver is designed and implemented. 2. Sending module: The function of sending module is to send parallel 8-bit data in serial form, each group of serial data plus parity bits, start bits and stop bits. 3. Receiving module: The function of receiving module is to receive serial data output by sending module and send data to memory in parallel.
Plat: Verilog | Size: 5232KB | Downloads: 0
pandaxiong 2019-03-22 22:59:14
Description: The Dpsk non-correlation demodulation FPGA code can search the synchronization point for non-correlation demodulation, including the whole project project, and can be directly opened in ISE for simulation and testing.
Plat: Verilog | Size: 11504KB | Downloads: 0
Zhongzi123 2019-03-22 22:26:43
Description: Spi serial output ADC - AD7989 Verilog source code.
Plat: Verilog | Size: 1KB | Downloads: 0
Zhongzi123 2019-03-22 22:24:20
Description: AXI4-Lite Bus Host-Slave Read-Write, Routine and Code
Plat: Vivado | Size: 12186KB | Downloads: 0
Zhongzi123 2019-03-22 22:20:38
Description: 18-bit successive approximation serial ADC LTC2379 IP core, VHDL
Plat: VHDL | Size: 1KB | Downloads: 0
Zhongzi123 2019-03-22 22:04:46
Description: 14-bit 125MSPS high-speed ADCLTC2145 IP core, VHDL language
Plat: VHDL | Size: 4KB | Downloads: 0
PC130 2019-03-22 11:20:58
Description: Temperature and humidity data acquisition routine using DHT11 sensor on FPGA
Plat: VHDL | Size: 13666KB | Downloads: 0
OneHund 2019-03-21 21:54:07
Description: The implementation of VHDL code decoded by H264 is simulated on MODELSIM.
Plat: VHDL | Size: 7455KB | Downloads: 2
q684351852 2019-03-20 19:25:23
Description: I2C verilog code I2C (Inter-Integrated Circuit)
Plat: Verilog | Size: 5KB | Downloads: 0
attentionjj 2019-03-20 16:13:50
Description: The amplitude and frequency of triangular wave, sawtooth wave, square wave and sine wave can be correctly displayed on the oscilloscope
Plat: VHDL | Size: 4186KB | Downloads: 0
attentionjj 2019-03-20 16:01:54
Description: Realization of Picture Display by VGA,This includes VGA timing and data stored in ROM.
Plat: Verilog | Size: 7524KB | Downloads: 0
truongphamhsht@97 2019-03-20 14:58:22
Description: fft for 64 point pipeline
Plat: VHDL | Size: 1795KB | Downloads: 1
wudw 2019-03-20 00:56:00
Description: The coordinate transformation is realized by CORDIC
Plat: Verilog | Size: 1KB | Downloads: 0
快乐风男123 2019-03-19 19:10:19
Description: 16-bit sin and COS function generators are realized, and the time series simulation of modeldim is successful.
Plat: VHDL | Size: 18583KB | Downloads: 0
ThreeJ 2019-03-19 18:23:02
Description: The test file of PFGA LED lamp is very useful.
Plat: Quartus II | Size: 2922KB | Downloads: 0
ThBryan 2019-03-19 13:38:29
Description: Verilog Driver of Classic OV5642
Plat: Verilog | Size: 171KB | Downloads: 4
ThBryan 2019-03-19 13:36:05
Description: Reference Code of ICMP Protocol Implemented by Classical Verilog Language
Plat: Verilog | Size: 979KB | Downloads: 0
ThBryan 2019-03-19 13:32:59
Description: Code of Inverted FIR Filter Implemented by Classical Verilog Language
Plat: Verilog | Size: 260KB | Downloads: 0
akki1234 2019-03-19 01:46:00
Description: ADDER VLSI IMPLEMETATION CARRY SKIP ADDER IN VERILOG
Plat: Verilog | Size: 35KB | Downloads: 0
akki1234 2019-03-19 01:35:37
Description: ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
Plat: Verilog | Size: 32KB | Downloads: 0
datou_2002 2019-03-18 18:14:45
Description: Implementation of high-speed multi-channel synchronous serial port by FPGA
Plat: Others | Size: 4KB | Downloads: 2
柚子黑贤 2019-03-17 17:11:17
Description: Sobel image detection
Plat: Verilog | Size: 18835KB | Downloads: 0
chanducs 2019-03-17 15:29:33
Description: advanced encryiption algorithm
Plat: Verilog | Size: 19KB | Downloads: 0
九祈 2019-03-17 14:49:14
Description: Design of m-Sequence Generator
Plat: Verilog | Size: 31KB | Downloads: 0
上下文 2019-03-16 12:28:39
Description: Digital Clock The digital clock designed by AD contains PCB mapping and uses the Texas Instrument Device Library.
Plat: Altium | Size: 3072KB | Downloads: 0
分快 2019-03-16 02:52:26
Description: FPGA implementation of QPSK
Plat: Verilog | Size: 1KB | Downloads: 0
Tags: