AcaOph 2020-11-25 22:44:14
Description: Counter,counting function
Plat: Verilog | Size: 69KB | Downloads: 0
Zaner 2020-11-25 14:23:50
Description: Arm official cm0 novice learning course
Plat: Verilog | Size: 4180KB | Downloads: 0
hqp_lhkfw 2020-11-24 22:29:54
Description: AD4111 datasheet,English,16 channel
Plat: C/C++ | Size: 971KB | Downloads: 0
ancirl 2020-11-24 18:03:54
Description: a drive using FPGA and microcontroller technology. The process data channel is very time critical. This functionality should be realized in h
Plat: VHDL | Size: 301KB | Downloads: 0
ancirl 2020-11-24 17:57:27
Description: This is read by the CPLD Development absolute encoder feedback s
Plat: HTML | Size: 12KB | Downloads: 0
ancirl 2020-11-24 17:55:02
Description: Directory: VHDL-FPGA-Verilog Plat: VHDL Size: 27KB
Plat: Python | Size: 15KB | Downloads: 0
ancirl 2020-11-24 17:51:27
Description: FPGA VHDL DATA DIVIVER 2.23
Plat: VHDL | Size: 6KB | Downloads: 0
ancirl 2020-11-24 17:50:21
Description: QUARTUS2 16.9 VHDL FPGA ENDAT2.2
Plat: Quartus II | Size: 4KB | Downloads: 0
ancirl 2020-11-24 17:46:39
Description: VHDL BISS,SSI,ENDAT2.2, ENCODER
Plat: Verilog | Size: 36KB | Downloads: 0
ryan.park 2020-11-24 12:59:07
Description: proteus project - high pass filter
Plat: C/C++ | Size: 14KB | Downloads: 0
ryan.park 2020-11-24 12:52:38
Description: proteus project - low pass filter
Plat: C/C++ | Size: 79KB | Downloads: 0
ryan.park 2020-11-24 12:47:06
Description: proteus project file to create sub circuit
Plat: C/C++ | Size: 26KB | Downloads: 0
飞扬飘逸 2020-11-24 12:39:39
Description: DMA code based on hbird_e203 system
Plat: VHDL | Size: 6KB | Downloads: 0
Aaron_liu1223 2020-11-24 10:51:04
Description: Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.
Plat: Quartus II | Size: 5KB | Downloads: 0
mioaf 2020-11-23 22:00:44
Description: Ad5755 VHDL programming source code ad5755 VHDL programming source code
Plat: VHDL | Size: 30KB | Downloads: 0
CrazyICer 2020-11-23 17:58:17
Description: Xilinx's QDMA related driver problem solving manual, you can refer to when developing the driver
Plat: PDF | Size: 722KB | Downloads: 0
路月生 2020-11-23 15:59:41
Description: Frequency divider,Four clocks for counting control are generated, and the pulses with different frequencies are obtained by modifying the parameters.
Plat: VHDL | Size: 1KB | Downloads: 0
tariq 2020-11-23 13:44:09
Description: A commonly used method to achieve contrast enhancement is histogram equalization(HE), which enhances the global contrast of the image
Plat: VHDL | Size: 4112KB | Downloads: 0
DADFJKAF 2020-11-22 21:43:35
Description: In this design, a 16 bit binary adder designed in time sequence is composed of 3 stages of pipelined 16 bit adder, hexadecimal addition counter and 16 bit three state control gate circuit. This design is a 3-stage pipeline design, which increases the delay of the inserted registers and the time difference of signal synchronization, but it can improve the overall running speed. In use, you only need to input the addend and the addend. Press the first equal key to save the first addition result. Press the second equal key to get the first addition result. At the same time, store the second result. Press the third equal key to get the result of the second addition. The result is stable and can meet the design requirements of pipelined 16 bit add
Plat: VHDL | Size: 5883KB | Downloads: 0
万语深渊 2020-11-22 21:37:48
Description: Implementation of D flip flop
Plat: Verilog | Size: 32KB | Downloads: 0
tariq 2020-11-21 17:07:41
Description: sobel kernel will compute the sobel gradient of the tile
Plat: VHDL | Size: 3KB | Downloads: 0
Hu_Jiao 2020-11-21 15:43:34
Description: DE2 tutorial, Using the SDRAM Memory on Altera's DE2 Board with Verilog Design
Plat: Quartus II | Size: 382KB | Downloads: 0
李宇春1 2020-11-21 09:25:21
Description: Implementation of 32-bit CRC verification module
Plat: Verilog | Size: 1KB | Downloads: 0
oo4285 2020-11-20 18:38:46
Description: ML403 Embedded MicroBlaze Reference Design
Plat: VHDL | Size: 870KB | Downloads: 0
yunzhiying 2020-11-20 17:27:46
Description: I2C verilog code, it is a simple I2C project includes doc
Plat: Verilog | Size: 1398KB | Downloads: 0
热情冰点 2020-11-20 16:47:12
Description: NRZ decoding program, Verilog language in CPLD implementation
Plat: Verilog | Size: 2001KB | Downloads: 0
蛋蛋崽仔 2020-11-20 13:29:23
Description: Realization of flow lamp with MSP430G2553
Plat: C/C++ | Size: 19KB | Downloads: 0
00788888 2020-11-19 22:26:34
Description: It is convenient to use can protocol to SPI interface. It is convenient to use can protocol to SPI interface.
Plat: Quartus II | Size: 16KB | Downloads: 0
gieng 2020-11-19 09:55:42
Description: Programming course of hardware circuit description language
Plat: Quartus II | Size: 9870KB | Downloads: 0
dfdfa 2020-11-19 03:15:20
Description: When using asynchronous signals, a good design will perform synchronous processing on asynchronous signals. Synchronization generally uses multi-level D flip-flop cascade processing, as shown in the figure below. Most of the data of this model say that after the first-level register generates a metastable state, the second-level register has a stable output probability of 90%, and the third-level register has a stable output probability of 99%. If the metastable state follows the circuit, Pass it on, and the system with weaker self-repair ability will directly collapse.
Plat: Verilog | Size: 2KB | Downloads: 0
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