妄祭 2019-12-08 23:00:39
Description: I2C communication code implemented by Verilog
Plat: Video | Size: 5715KB | Downloads: 0
陌陌沫沫 2019-12-08 16:15:28
Description: Quantization and zigzag coding in image compression
Plat: VHDL | Size: 2KB | Downloads: 0
datangel 2019-12-06 17:03:21
Description: IEEE Standard Verilog Hardware Description Language
Plat: Visual C++ | Size: 2141KB | Downloads: 0
godgaoying 2019-12-06 14:56:40
Description: Learning FPGA must be practical
Plat: Verilog | Size: 17382KB | Downloads: 0
Rick2809 2019-12-06 04:59:12
Description: Multiplexers are combinational circuits with several inputs and a single data output. They are equipped with control inputs capable of selecting one, and only one, of the data inputs to allow their transmission from the selected input to said output.
Plat: Vivado | Size: 106KB | Downloads: 0
vaclavpe 2019-12-05 20:32:55
Description: risc 8 by coonan compatible with PIC16C57
Plat: Verilog | Size: 80KB | Downloads: 0
Jank1 2019-12-05 19:08:04
Description: File testing, please download carefully, if there is a problem, please advise, do not spray.
Plat: Verilog | Size: 3KB | Downloads: 0
Jayakishan 2019-12-05 18:39:53
Description: VLSI Implementation of comb
Plat: PDF | Size: 587KB | Downloads: 0
Jayakishan 2019-12-05 18:05:56
Description: Comb filter implementation in verilog
Plat: PDF | Size: 808KB | Downloads: 0
Jayakishan 2019-12-05 18:03:27
Description: FPGA implementation of DSP circuit
Plat: PDF | Size: 1948KB | Downloads: 0
qduxin 2019-12-05 16:29:33
Description: Using FPGA to config SONY IMX264 CMOS image sensor through SPI interface
Plat: Verilog | Size: 3KB | Downloads: 1
陌路寻香 2019-12-05 16:27:24
Description: RISC-v large-scale many-core project, the architecture supports 500 million cores, adopts distributed cache coherence, transplants ARRIANE core for optimization, and 2-dimensional tiled network
Plat: VHDL | Size: 10593KB | Downloads: 0
dinuroy 2019-12-04 13:33:31
Description: ahb master using verilog
Plat: Verilog | Size: 903KB | Downloads: 0
jackson@qq 2019-12-03 23:02:02
Description: The problem of risc-v can be solved
Plat: C/C++ | Size: 35KB | Downloads: 0
百花筒 2019-12-03 18:02:52
Description: FPGA completes the manual setting of timing parameter 0-99 and countdown
Plat: Verilog | Size: 735KB | Downloads: 0
z534925714 2019-12-03 15:30:05
Description: Based on Verilog taximeter, Quartus ii9.1 (32 bit) software is used
Plat: VHDL | Size: 5KB | Downloads: 0
VISON豪 2019-12-03 14:17:37
Description: IIC bus transmission code, including relevant simulation
Plat: Verilog | Size: 9863KB | Downloads: 0
赵东001 2019-12-02 19:06:44
Description: A data transmission system with typical functions of BP protocol (Overtime retransmission mechanism and managed transmission) consists of five nodes
Plat: Verilog | Size: 180KB | Downloads: 0
老田. 2019-12-02 16:37:09
Description: VerilogHDL schedule is realized, seven segments display hour / minute / second.
Plat: Verilog | Size: 3KB | Downloads: 0
luzhouxue 2019-12-02 15:31:14
Description: VGA display control code based on FPGA
Plat: Verilog | Size: 16413KB | Downloads: 0
一坨翔的心情 2019-12-02 11:59:06
Description: The Vivado concise tutorial, including the Viado's use tutorial, and the Verilog syntax knowledge.
Plat: Others | Size: 4551KB | Downloads: 0
东山游客 2019-12-02 09:29:12
Description: Modify the system clock output frequency to any value by changing the parameters of PLL
Plat: VHDL | Size: 3048KB | Downloads: 0
金咕咕 2019-12-01 20:07:38
Description: The code of a tracking car based on single chip microcomputer can be directly opened with keil and burned in
Plat: C/C++ | Size: 3127KB | Downloads: 0
Ozol 2019-12-01 14:38:49
Description: Simple small program that can detect sequences, use on KX development board, enter manually
Plat: Verilog | Size: 6371KB | Downloads: 0
vivian_huo 2019-12-01 10:12:12
Description: The introduction experiment of Verilog LED
Plat: Verilog | Size: 5539KB | Downloads: 0
天之涯333 2019-11-30 19:18:46
Description: HK business leader criticizes US passage of HK act Father gets death for killing student Three hurt in knife attack in Dutch city Four Hebei cities hit by air pollution Sports industry investment fund eyed Party leadership over SOEs urged An important meeting chaired by Xi Jinping, general secretary of the Communist Party of China Central Committee, stresses the need to bolster the Party's leadership over State-owned enterprises and make the State-owned sector more competitive and influentia
Plat: Perl | Size: 25KB | Downloads: 0
我不会代码啊 2019-11-30 17:33:47
Description: An example of color image to gray image based on FPGA
Plat: VHDL | Size: 12857KB | Downloads: 0
谷雨429 2019-11-30 15:28:26
Description: Using quartus software programming, the following functions are realized in the EDA development board of DE2-70: a switch device is designed. When the button K is pressed for the first time, the three lights x, y and Z are on at the same time; when the button K is pressed again, the X light is off immediately; when the Y light is off 5 s later, the Z light is off 8 s later.
Plat: VHDL | Size: 1260KB | Downloads: 0
asdfghjklqaz 2019-11-30 13:31:14
Description: generate number by LFSR
Plat: Verilog | Size: 102KB | Downloads: 0
kiemsi 2019-11-28 16:38:53
Description: DVB-S2 transmitter in GNURadio
Plat: Python | Size: 1830KB | Downloads: 0
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