LYL_COC 2018-11-15 16:44:52
Description: CY7C6801XA FPGA Source code
Plat: Verilog | Size: 3579KB | Downloads: 0
LYL_COC 2018-11-15 16:39:11
Description: AD9361 verilog_gw300-master
Plat: Verilog | Size: 54KB | Downloads: 0
LYL_COC 2018-11-15 16:35:20
Description: wimax ofdm system code
Plat: Verilog | Size: 1162KB | Downloads: 0
LYL_COC 2018-11-15 16:32:20
Description: dvbt cofdm system code
Plat: VHDL | Size: 6048KB | Downloads: 0
LYL_COC 2018-11-15 16:04:00
Description: OFDM system VHDL code
Plat: VHDL | Size: 1396KB | Downloads: 0
LYL_COC 2018-11-15 15:56:44
Description: OFDM system VHDL code
Plat: VHDL | Size: 71KB | Downloads: 0
Park_sc 2018-11-15 10:31:48
Description: The universal complement conversion original code, or the original code conversion complement format, can configure the bit width.
Plat: Verilog | Size: 710KB | Downloads: 0
Park_sc 2018-11-15 10:12:55
Description: The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design.
Plat: Verilog | Size: 5660KB | Downloads: 0
绣源 2018-11-14 22:07:21
Description: FPGA sequencing and DDS generate various waveform programs.
Plat: Verilog | Size: 6563KB | Downloads: 0
zzx_nb 2018-11-14 21:04:55
Description: ADS1256 driver code, written in Verilog, runs successfully on quartus.
Plat: Quartus II | Size: 8512KB | Downloads: 3
青春祭 2018-11-14 18:11:04
Description: Two cases of sequential detector function using finite state machine and shift register respectively.
Plat: VHDL | Size: 776KB | Downloads: 0
小先生2018 2018-11-14 15:50:34
Description: The image scaling module is made by double three convolution.
Plat: Verilog | Size: 22KB | Downloads: 8
Yasuri Nanami 2018-11-14 14:53:07
Description: FX3, as the core of the FPGA Slave, completes the communication validation routines with PC. The pins need to be configured according to their own FX3 development board. The default configuration is HSC's ALTERA development board, EP4CE22F17C8+CYUSB3014.Synchronous FIFO transmission is verified by CyConsole. SignalTapII waveform is attached.
Plat: Verilog | Size: 11337KB | Downloads: 1
tosaodjao 2018-11-14 13:04:38
Description: The hex counter is designed as vhdl. I hope it helps a lot.
Plat: VHDL | Size: 66KB | Downloads: 0
Mola998 2018-11-14 00:07:59
Description: FPGA based signal generator, using DDS frequency synthesis to generate multiple waveforms.
Plat: Verilog | Size: 6241KB | Downloads: 0
zq729 2018-11-13 23:19:11
Description: LCD control VHDL program and simulation
Plat: VHDL | Size: 4KB | Downloads: 0
zq729 2018-11-13 23:13:51
Description: FPGA driver LED static display
Plat: VHDL | Size: 5KB | Downloads: 0
harini 2018-11-13 18:43:42
Description: hi any one know this file please use this
Plat: matlab | Size: 25KB | Downloads: 0
命若琴弦 2018-11-13 11:36:30
Description: Frequency division of 50MHz input signal of test board
Plat: Verilog | Size: 54KB | Downloads: 0
苏_sir 2018-11-13 09:50:42
Description: Beginners information, learning VHDL good tutorial, a classic practical tutorial
Plat: VHDL | Size: 165KB | Downloads: 0
charlees 2018-11-13 04:34:20
Description: basys3 board project. fpga. vhdl code. Probably seven segment.
Plat: VHDL | Size: 6KB | Downloads: 0
charlees 2018-11-13 04:32:49
Description: vhdl code. helpful. vhdl project.
Plat: VHDL | Size: 513KB | Downloads: 0
charlees 2018-11-13 04:31:55
Description: VHDL verilog useful for school labs. eee.
Plat: VHDL | Size: 504KB | Downloads: 0
charlees 2018-11-13 04:30:56
Description: VHDL code for lab. Useful and easy.
Plat: VHDL | Size: 364KB | Downloads: 0
charlees 2018-11-13 04:27:42
Description: It's a VHDL project. Useful for school and labs.
Plat: Vivado | Size: 567KB | Downloads: 0
Christhian 2018-11-12 22:48:37
Description: gmsk modulator modules
Plat: VHDL | Size: 1KB | Downloads: 0
Christhian 2018-11-12 22:45:36
Description: GMSK vhdl generated from simulink
Plat: VHDL | Size: 39KB | Downloads: 0
sherex 2018-11-12 19:30:03
Description: this is what i wanna share
Plat: Pascal | Size: 5631KB | Downloads: 0
Rahena 2018-11-12 15:18:58
Description: sixteen bit ALU using spice software
Plat: Spice | Size: 13125KB | Downloads: 0
芒果桃 2018-11-12 13:04:46
Description: Digital stopwatch ,Digital stopwatchDigital stopwatchDigital stopwatch
Plat: VHDL | Size: 271KB | Downloads: 0
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