sadfcdxvxvfg 2019-07-21 15:19:18
Description: The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.
Plat: VHDL | Size: 4787KB | Downloads: 0
哈嘿huhu 2019-07-20 22:48:28
Description: The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.
Plat: matlab | Size: 4KB | Downloads: 0
木示 2019-07-20 08:58:41
Description: Fast fft own procedures, faster than the system call fft slowe
Plat: C/C++ | Size: 18KB | Downloads: 0
may0911 2019-07-20 01:53:00
Description: Yulgang latest plug-in needed to download, games happy)
Plat: Java | Size: 1521KB | Downloads: 0
人从 2019-07-19 21:22:13
Description: EMIF interface test program for FIFO and DSP of FPGA
Plat: Verilog | Size: 5028KB | Downloads: 0
孤独小岛 2019-07-19 20:49:41
Description: Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.
Plat: Verilog | Size: 3029KB | Downloads: 0
xiaozi123 2019-07-18 13:06:35
Description: Run lenet-5 on zedboard
Plat: C/C++ | Size: 12903KB | Downloads: 0
msli121 2019-07-18 11:03:34
Description: Implementation of Simple Pipeline CPU Verilog
Plat: VHDL | Size: 17KB | Downloads: 0
摩羯的而已 2019-07-18 10:54:55
Description: Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.
Plat: Verilog | Size: 27KB | Downloads: 0
ssrsgs 2019-07-18 10:47:25
Description: Simple uart, Verilog language, has been tested, you can see if you need it
Plat: Verilog | Size: 3KB | Downloads: 0
mingxing1 2019-07-18 08:33:45
Description: the program for LCD1602 based on Verilog HDL
Plat: Verilog | Size: 5514KB | Downloads: 0
tanbour 2019-07-17 22:59:19
Description: One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.
Plat: Verilog | Size: 4783KB | Downloads: 0
SherryDong 2019-07-17 21:56:19
Description: Realization of Serial Communication and SLIP Protocol
Plat: Verilog | Size: 8727KB | Downloads: 0
asjdiojatesttesttest 2019-07-17 21:25:28
Description: this is a thing to do a thing C++ rar
Plat: C# | Size: 4KB | Downloads: 0
zhongjuncd55 2019-07-17 17:26:48
Description: LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.
Plat: Verilog | Size: 7KB | Downloads: 1
xsac 2019-07-17 16:12:31
Description: The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.
Plat: Verilog | Size: 583KB | Downloads: 0
xsac 2019-07-17 16:10:35
Description: Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module
Plat: Verilog | Size: 498KB | Downloads: 0
xsac 2019-07-17 16:08:16
Description: A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.
Plat: VHDL | Size: 701KB | Downloads: 0
xsac 2019-07-17 16:05:26
Description: This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay
Plat: VHDL | Size: 644KB | Downloads: 0
xsac 2019-07-17 15:59:52
Description: The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.
Plat: VHDL | Size: 543KB | Downloads: 0
陈一12 2019-07-17 13:30:54
Description: RISC 5 pipeline CPU with HAZARD processing
Plat: VHDL | Size: 3KB | Downloads: 0
richman 2019-07-17 10:37:10
Description: SHA256 Encryption/Decryption Verilog RTL Code
Plat: VHDL | Size: 124KB | Downloads: 0
olmas 2019-07-17 07:43:05
Description: (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig
Plat: Verilog | Size: 20707KB | Downloads: 0
yhoo 2019-07-16 20:28:14
Description: ADC Reference code!Clock 100kHz
Plat: Others | Size: 1446KB | Downloads: 0
loghman 2019-07-16 19:27:13
Description: Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
Plat: matlab | Size: 2KB | Downloads: 0
fregi5 2019-07-16 19:02:25
Description: DS1302 clock driver, which has been verified on quartus, can be used directly
Plat: Verilog | Size: 5004KB | Downloads: 0
cbcbcbcb 2019-07-16 17:00:14
Description: VHDL common small experiment code
Plat: VHDL | Size: 3KB | Downloads: 0
lulu72469 2019-07-16 16:01:45
Description: FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc.
Plat: Verilog | Size: 2035KB | Downloads: 0
tp007 2019-07-16 14:19:48
Description: This is code of UVM CALLBACK function.
Plat: Verilog | Size: 164KB | Downloads: 0
ted.1234 2019-07-16 11:25:19
Description: this is mouse linux code
Plat: LINUX | Size: 130KB | Downloads: 0
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