Nolan1878 2019-10-14 13:50:59
Description: RISC Reduced Instruction Set Computer can execute more instructions in one clock cycle than CISC Complex Instruction Set Computer. These instructions are shorter, simpler and more uniform than CISC Instruction Set. Therefore, RISC Reduced Instruction Set Computer is suitable for pipeline processing and speeds up the processing speed.
Plat: Verilog | Size: 7322KB | Downloads: 0
小白侯 2019-10-11 14:52:40
Description: Relevant Data for Realizing Programming on FPGA
Plat: VHDL | Size: 4402KB | Downloads: 0
dxayvlf 2019-10-11 10:14:15
Description: an iic slave sample. can use by FPGA
Plat: Verilog | Size: 7KB | Downloads: 0
dxayvlf 2019-10-11 10:10:34
Description: record the time by uart
Plat: Verilog | Size: 2KB | Downloads: 0
wwei123 2019-10-10 10:01:19
Description: Standard IIC communication interface, master and slave, up to 1mHz
Plat: VHDL | Size: 2KB | Downloads: 1
assa127 2019-10-09 18:02:14
Plat: Verilog | Size: 485KB | Downloads: 0
A621135 2019-10-08 15:35:22
Description: The SDSPI controller offered here exports an high level SD card interface to the rest of an FPGA core via a wishbone bus. Interaction at the lower level is accomplished via SPI. Unlike the other SD card controller available here on Open Cores which operates using the full bi-directional SD interface, this core uses the SPI interface to the core. While this is a slower interface, the SPI interface is necessary when accessing the card on a XuLA2 board (for example), or in general any time the full 9-bit, bi-directional interface has not been implemented. Further, for those who are die-hard Verilog authors, this core is written in Verilog as opposed to the XESS provided demonstration SD card controller found on GitHub, which was written in VHDL.
Plat: Verilog | Size: 275KB | Downloads: 0
A621135 2019-10-08 15:24:00
Description: Data transmission through the iic bus, this part is host module and slave module, can be converted to each other, no simulation.
Plat: Verilog | Size: 4449KB | Downloads: 0
A621135 2019-10-08 15:22:14
Description: Data transmission through the iic bus, this part is the host module, no simulation.
Plat: Verilog | Size: 1444KB | Downloads: 0
A621135 2019-10-08 15:20:45
Description: Data transmission through the iic bus, this part is from the machine module, no simulation.
Plat: Verilog | Size: 1266KB | Downloads: 0
A621135 2019-10-08 15:04:32
Description: Through the iic bus to achieve data reading and writing,and based on the modelsim test.
Plat: Vivado | Size: 9KB | Downloads: 1
Dr.stone 2019-10-05 20:14:35
Description: Kalman filter library, adjustable parameters to reach the optimal, has been verified and used in engineering applications
Plat: C/C++ | Size: 3KB | Downloads: 0
CrazyICer 2019-10-05 12:09:15
Description: Camera+Link protocol and the design of digital image signal source based on FPGA are good design papers for reference and learning.
Plat: PDF | Size: 256KB | Downloads: 0
Eric_DZ 2019-10-03 22:57:32
Description: 3-8encoder,Based on Verilog implementation,the primary program
Plat: Verilog | Size: 3KB | Downloads: 0
ForEverQ 2019-10-03 22:33:05
Description: amba spec very detailed specification
Plat: WINDOWS | Size: 874KB | Downloads: 0
nimish25 2019-10-03 11:25:04
Description: Implementing MUX using Case statement in VHDL
Plat: VHDL | Size: 6KB | Downloads: 0
loveAlex 2019-10-01 09:10:45
Description: Design Ideas of Single Cycle CPU
Plat: Quartus II | Size: 527KB | Downloads: 0
Great_Toufu 2019-09-29 16:51:54
Description: uart accomplished in verilog language
Plat: Verilog | Size: 1KB | Downloads: 1
flyons 2019-09-29 16:03:20
Description: This material describes the grammatical rules of the hardware language of FPGA, which is of great help to beginners. This book is only for the reference of enthusiasts and should not be illegally disseminated.
Plat: Verilog | Size: 1475KB | Downloads: 1
joy0 2019-09-29 13:23:15
Description: DRAM simulation model
Plat: Verilog | Size: 398KB | Downloads: 0
fpga—yang 2019-09-27 20:01:19
Description: The computer sends different commands through the serial port, which includes the configuration of check and baud rate
Plat: VHDL | Size: 6KB | Downloads: 0
fpga—yang 2019-09-27 19:56:46
Description: Serial port receiving and sending
Plat: VHDL | Size: 3KB | Downloads: 0
tozoti_1985 2019-09-25 21:59:07
Description: Micron 512Mb SDRAM Verilog model
Plat: Verilog | Size: 6KB | Downloads: 0
Parvathy 2019-09-25 19:45:04
Description: verilog code for counter with additional signal going high at a particular count
Plat: Verilog | Size: 10KB | Downloads: 0
Parvathy 2019-09-25 19:40:09
Description: Verilog code for implementing simple ALU.
Plat: Verilog | Size: 39KB | Downloads: 0
eng_mohamed 2019-09-25 07:01:08
Description: spi code interface for cimmunicaton
Plat: Python | Size: 270KB | Downloads: 0
eng_mohamed 2019-09-25 06:51:06
Description: multiplexer and demultiplexer verilog code
Plat: Vivado | Size: 395KB | Downloads: 0
tuyenth 2019-08-21 13:13:55
Description: Tiny FPGA code for programming Lattice FPGA
Plat: Verilog | Size: 606KB | Downloads: 1
dianfeng1995 2019-08-21 09:56:42
Description: Frequency meter, also known as frequency counter, is an electronic measuring instrument specially for measuring the frequency of the signal under test. Frequency meter, Verilog code implementation.
Plat: Verilog | Size: 15809KB | Downloads: 0
sudochang 2019-08-21 09:35:41
Description: The function of signal generator is realized based on FPGA, which is a good reference.
Plat: Verilog | Size: 2534KB | Downloads: 2