LIN东 2021-02-27 14:17:15
Description: DIGITAL FILTER FPGA design knowledge, sample program information
Plat: Verilog | Size: 23198KB | Downloads: 0
早睡觉 2021-02-27 03:10:08
Description: handy Verilog tutorial, newbie friendly.
Plat: VHDL | Size: 636KB | Downloads: 0
andreac 2021-02-27 00:00:06
Description: SPI master and Slave in VHDL
Plat: VHDL | Size: 184KB | Downloads: 0
andreac 2021-02-26 23:59:05
Description: CRC parallel and serial implementation in VHDL
Plat: VHDL | Size: 566KB | Downloads: 0
andreac 2021-02-26 23:57:14
Description: True Random Number Generator in verilog
Plat: Verilog | Size: 55KB | Downloads: 0
andreac 2021-02-26 23:56:00
Description: Waveform generator and sin/cos LUT VHDL module
Plat: VHDL | Size: 193KB | Downloads: 0
andreac 2021-02-26 23:53:48
Description: Zero Bus Turnaround SRAM VHDL controller
Plat: VHDL | Size: 389KB | Downloads: 0
yao.g 2021-02-26 13:11:46
Description: I2C code can been syn and simulation ,veritify
Plat: Verilog | Size: 6KB | Downloads: 0
fyrfyr 2021-02-25 10:12:16
Description: The board is used to upload a string of characters per second. If the characters are sent to the board, the same characters will be returned.
Plat: Vivado | Size: 726KB | Downloads: 0
bigpin2021 2021-02-23 17:45:34
Description: The receiver is a serial receiving module, receiving from serial port receives the serial data sent by the host computer, and gives a notification signal after receiving a frame of data (8 bits) done. The Sender is the serial port sending module, is the core. In order to send the enable signal, the received data is data send port through serial port is sent out. It should be noted that there are two variables defined in the top module, system clock frequency Freq and BPS is used according to the different system clock frequency and the required serial port baud rate. We can try to the serial port baud is set to other values (such as 9600). When the module is instantiated, this variable will be passed to the serial port receiving and sending module, so as to achieve different rates of serial communication.
Plat: C/C++ | Size: 2KB | Downloads: 0
maxiaojun 2021-02-23 11:40:13
Description: h-bridge power cell cpld code
Plat: VHDL | Size: 2KB | Downloads: 0
pppgq 2021-02-23 10:31:54
Description: User manual of Ziguang Tongchuang development board pg22l
Plat: Verilog | Size: 2886KB | Downloads: 0
mmpw 2021-02-22 21:55:35
Description: It is used to drive Sony's area array CCD, and is designed with timing logic
Plat: Verilog | Size: 1KB | Downloads: 0
chooseboy 2021-02-22 13:40:24
Description: Tsmc18, design documents, for reference only, I feel it is helpful for learning
Plat: Verilog | Size: 22KB | Downloads: 0
bdmded 2021-02-22 03:41:22
Description: tv _box_demonstration DE2-115
Plat: Verilog | Size: 8424KB | Downloads: 0
时光乄星河 2021-02-18 09:58:06
Description: It mainly includes I2C master, slave module, and a simple SIM file
Plat: LINUX | Size: 5KB | Downloads: 2
12345648919 2021-02-18 08:31:11
Description: ldpc encode cuda can be used
Plat: C/C++ | Size: 4064KB | Downloads: 0
excellency00 2021-02-18 06:13:56
Description: counter project basys3 board
Plat: VHDL | Size: 920KB | Downloads: 0
dan9U 2021-02-18 01:23:12
Description: ARRL_Lab_test_Procedure Manual 2015 with page breaks
Plat: WINDOWS | Size: 1711KB | Downloads: 0
jamimu 2021-02-17 03:35:37
Description: radix 5 adder
Plat: Vivado | Size: 665KB | Downloads: 0
jamimu 2021-02-17 03:32:38
Description: fifo
Plat: Vivado | Size: 17577KB | Downloads: 0
打包搬家 2021-02-15 10:23:10
Description: zedboard,Verilog,vivado/.
Plat: Verilog | Size: 3438KB | Downloads: 0
sydy110 2021-02-11 12:11:43
Description: An FPGA Based Software Defined Radio Platform for the 24GHz ISM Band
Plat: C/C++ | Size: 2706KB | Downloads: 1
Saske 2021-02-09 02:01:58
Description: VHDL code showing a 8 to 3 encoder
Plat: VHDL | Size: 4512KB | Downloads: 0
Saske 2021-02-09 02:00:29
Description: VHDL code showing a 4 to 2 encoder
Plat: VHDL | Size: 146KB | Downloads: 0
Saske 2021-02-09 01:59:39
Description: VHDL code showing a 2 to 1 encoder
Plat: VHDL | Size: 4470KB | Downloads: 0
Saske 2021-02-09 01:56:44
Description: VHDL code showing an ALU_4bits
Plat: VHDL | Size: 4461KB | Downloads: 0
Saske 2021-02-09 01:54:04
Description: VHDL code showing an ALU_General
Plat: VHDL | Size: 99KB | Downloads: 0
henry~z 2021-02-09 00:25:23
Description: 32*32 floating multiplication matrix
Plat: Verilog | Size: 1KB | Downloads: 2
anl1984 2021-02-08 20:09:20
Description: Test input and output, communication test, control test, analog input and output.
Plat: Arduino | Size: 112KB | Downloads: 1
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