彭瑾 2017-09-22 17:10:48
Description: crc search .12bit_4bit,8_8bit,and16 bit_8bit,32bit_8bit progranming by verilog languages,is very good. I think is correct
Plat: Verilog | Size: 6KB | Downloads: 0
刘宗明 2017-09-22 17:09:51
Description: Relief computing classification weight, Complete codec LDPC code, Bottom-pass and band-pass FIR and IIR filter bottom pass and band-pass filter.
Plat: Python | Size: 58KB | Downloads: 0
郭星辰 2017-09-22 16:06:29
Description: Two choose one, for FPGA programming beginner stage, a simple example, the use of decompression can be, Quartus II 9 (32-Bit) applications
Plat: VHDL | Size: 144KB | Downloads: 0
hejie 2017-09-22 16:03:35
Description: Bayer to RGB source code, Verilog language, FPGA use,
Plat: Vivado | Size: 10KB | Downloads: 0
唐小芳 2017-09-22 14:56:36
Description: modelsim use tutorials, step by step, It is very detailed, especially for beginners.
Plat: Quartus II | Size: 378KB | Downloads: 0
吴峰 2017-09-22 14:45:04
Description: This document describes how to write SRAM in a hardware programming language called VHDL
Plat: VHDL | Size: 2682KB | Downloads: 0
卢文建 2017-09-21 16:38:11
Description: PCIE English help documentation, you can have a better understanding of PCIE
Plat: Quartus II | Size: 12872KB | Downloads: 1
卢文建 2017-09-21 16:35:47
Description: Using FPGA to achieve Ethernet transmission, communication mode is UDP
Plat: Quartus II | Size: 19398KB | Downloads: 0
张宇 2017-09-21 15:11:33
Description: The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available
Plat: Verilog | Size: 5811KB | Downloads: 0
张宇 2017-09-21 15:09:23
Description: The detailed analysis of the shift register, through concrete simulation and optimization, found that the code was fully available
Plat: Verilog | Size: 55KB | Downloads: 0
张宇 2017-09-21 15:07:25
Description: State machine basic engineering writing simulation and method, after specific simulation and optimization, find out the code is completely available
Plat: Verilog | Size: 4166KB | Downloads: 0
张宇 2017-09-21 15:05:09
Description: The method and simulation of the locking device are simulated and optimized, and the code is found to be fully available
Plat: Verilog | Size: 1KB | Downloads: 0
张宇 2017-09-21 15:02:37
Description: The method and simulation of the locking device are simulated and optimized, and the code is found to be fully available
Plat: Verilog | Size: 2724KB | Downloads: 0
张宇 2017-09-21 14:52:57
Description: I2C, test code, verified debugging and, this test code discovery is available
Plat: Verilog | Size: 1KB | Downloads: 0
tony 2017-09-20 21:57:40
Description: Xia Wenyu classic FPGA tutorial, hand taught you to learn FPGA
Plat: VHDL | Size: 1612KB | Downloads: 1
tony 2017-09-20 21:56:32
Description: FPGA classic tutorial, VHDL classic tutorial, from entry to the master
Plat: VHDL | Size: 28345KB | Downloads: 0
高军 2017-09-20 15:07:49
Description: Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry
Plat: VHDL | Size: 20KB | Downloads: 1
高军 2017-09-20 14:32:56
Description: To achieve three modes SPI master and slave module function design, data bit width 8bit, the maximum SPI clock frequency support 112MHz, using FSM design. Prepared by the pro test, used in Spartan6--45T series chips;
Plat: Verilog | Size: 2KB | Downloads: 2
xiwangtianye 2017-09-20 09:56:28
Description: Xilinx, Spartan-6, FPGA signal integrity Analytical simulation model
Plat: WINDOWS | Size: 7414KB | Downloads: 0
Seci 2017-09-20 02:07:04
Description: breast Cancer Classification
Plat: Java | Size: 19799KB | Downloads: 0
王宏 2017-09-19 19:48:24
Description: EMIF interface can be tested, including reading and writing two timing
Plat: Verilog | Size: 5318KB | Downloads: 0
张基拉 2017-09-19 17:13:26
Description: The book is devoted to the use of assertions, as well as to the syntax and examples of assertions
Plat: LINUX | Size: 203KB | Downloads: 1
元一份 2017-09-19 17:09:35
Description: Infrared communication based on FPGA
Plat: Verilog | Size: 8085KB | Downloads: 1
Vu 2017-09-19 16:16:12
Description: full adder 32 bit one you
Plat: C-C++ | Size: 749KB | Downloads: 0
Vu 2017-09-19 16:14:26
Description: full adder 4 bit one you
Plat: C-C++ | Size: 2KB | Downloads: 0
Vu 2017-09-19 16:07:35
Description: invalid description, it should be english
Plat: C-C++ | Size: 499KB | Downloads: 0
宇文炎 2017-09-19 15:02:44
Description: It is suitable for the parallel conversion module of MIPI-CSI2, which converts the image signals in RGB, YUV and other formats into serial data signals compatible with MIPI data channels
Plat: Vivado | Size: 1262KB | Downloads: 1
李晨 2017-09-19 13:01:38
Description: Verilog based I2C interface EEPROM 24lc64 testing procedures, including the virtual model of EEPROM, the actual hardware verification is no problem, you can also simulate through the modleism
Plat: Verilog | Size: 6KB | Downloads: 2
刘旭 2017-09-19 10:53:47
Description: Serial communication, support baud rate selection
Plat: Verilog | Size: 222KB | Downloads: 1
石志强 2017-09-18 22:57:18
Description: read bmp data to array ,used in video stream gen when sim
Plat: Verilog | Size: 2KB | Downloads: 1
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