fff 2017-07-29 03:04:19
Description: fyrytytrytryrtyrtgfhgfjfukrywetyjuurdhdsgdhgtrhyrtdyh
Plat: WINDOWS | Size: 30KB | Downloads: 0
parisa 2017-07-28 23:18:17
Description: VHDL code for CRC algorithm
Plat: VHDL | Size: 3892KB | Downloads: 0
李丹 2017-07-28 21:36:10
Description: Used to test the FPGA serial port reception, with singelTap. Convenient observation.
Plat: Verilog | Size: 6463KB | Downloads: 0
bi 2017-07-28 17:08:26
Description: Write your own FIR eight quit low-pass filter, for reference only
Plat: Verilog | Size: 6732KB | Downloads: 1
JQ 2017-07-28 15:00:31
Description: FPGA read the data of DS18B20
Plat: Verilog | Size: 7052KB | Downloads: 0
wang jiang 2017-07-28 14:47:36
Description: CY7C68013 FPGA control to achieve the USB interface communication, has passed the test
Plat: Verilog | Size: 3KB | Downloads: 0
wang jiang 2017-07-28 14:43:58
Description: Avgt development board based on the jesd204b source code
Plat: Verilog | Size: 7836KB | Downloads: 0
wang jiang 2017-07-28 14:26:30
Description: CY7C68013 firmware, FPGA test, Verilog
Plat: Verilog | Size: 194KB | Downloads: 0
合发 2017-07-28 09:35:02
Description: Face detection and tracking is an important and active research field, and it has a wide range of applications in video surveillance, biometrics, video coding and other fields. The goal of the project is to implement real-time systems on the FPGA board to detect and track faces. Face detection algorithms include skin segmentation and image filtering. The location of the human face is determined by calculating the centroid of the detected region. The software version of the algorithm is implemented independently and tested on MATLAB still images. Although the conversion from MATLAB to Verilog is not as smooth as expected, the experimental results demonstrate the accuracy and effectiveness of real-time systems, even in different light, facial gestures and color conditions. All hardware implementations are performed in real-time with minimal computational complexity and are therefore suitable for power constrained applications.
Plat: Verilog | Size: 62KB | Downloads: 0
潘武 2017-07-27 20:05:25
Description: Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode
Plat: Verilog | Size: 4600KB | Downloads: 0
詹俊凯 2017-07-27 10:27:36
Description: Dual Port Synchronization FIFO for ASIC/FPGA
Plat: Verilog | Size: 1KB | Downloads: 0
123456a2 2017-07-27 09:31:53
Description: fpga usb2.0 cy7c68013
Plat: VHDL | Size: 597KB | Downloads: 0
123456a2 2017-07-27 09:30:42
Description: fpga ddr3 sdram verilog
Plat: VHDL | Size: 7067KB | Downloads: 0
123456a2 2017-07-27 09:29:11
Description: fpga uart test xilinx
Plat: VHDL | Size: 380KB | Downloads: 0
123456a2 2017-07-27 09:27:58
Description: fpga key test xilinx
Plat: VHDL | Size: 190KB | Downloads: 0
123456a2 2017-07-27 09:26:22
Description: verilog led test xilinx
Plat: VHDL | Size: 2430KB | Downloads: 0
CH NVS RAVI TEJA 2017-07-26 23:22:24
Description: Verilog lab5 is used for learning vivado
Plat: Verilog | Size: 7KB | Downloads: 0
CH NVS RAVI TEJA 2017-07-26 23:21:24
Description: Verilog lab4 is used for learning vivado
Plat: Verilog | Size: 37KB | Downloads: 0
CH NVS RAVI TEJA 2017-07-26 23:20:28
Description: Verilog lab2 is used for learning vivado
Plat: Verilog | Size: 8KB | Downloads: 0
黄嫡 2017-07-26 16:22:46
Description: AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.
Plat: Verilog | Size: 4945KB | Downloads: 0
黄嫡 2017-07-26 16:11:40
Description: AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.
Plat: Verilog | Size: 1KB | Downloads: 0
David 2017-07-25 20:05:35
Description: SPI principle and its implemetation in verilog HDL
Plat: Verilog | Size: 24KB | Downloads: 0
2017-07-25 15:49:13
Description: FPGA code for driving TFT.
Plat: VHDL | Size: 530KB | Downloads: 0
zhanglong 2017-07-25 14:39:14
Description: simple program for SPI-Master
Plat: Verilog | Size: 1KB | Downloads: 0
nick 2017-07-25 10:57:30
Description: The program mainly to achieve FPGA serial communication, including source code and serial debugging tools
Plat: Verilog | Size: 768KB | Downloads: 1
杨成 2017-07-24 22:02:11
Description: This is a good tutorial for learning VHDL language. Very suitable for beginners to learn
Plat: VHDL | Size: 2855KB | Downloads: 1
liubing 2017-07-24 19:53:16
Description: Transform RGB data of a bmp to YUV.
Plat: Visual C++ | Size: 36KB | Downloads: 0
2017-07-24 16:43:22
Description: Axi_lite_user official sample, streamline function, apply to zynq series Axi bus
Plat: VHDL | Size: 4527KB | Downloads: 0
Tian Qing 2017-07-24 16:36:14
Description: Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.
Plat: VHDL | Size: 48571KB | Downloads: 0
han arima 2017-07-24 16:13:24
Description: Receive a 8 bit data through UART and display it on FPGA ego with LED
Plat: Verilog | Size: 696KB | Downloads: 0
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