Salkal 2020-01-21 11:48:30
Description: eeprom for stm8 arduino or stm
Plat: UNIX | Size: 241KB | Downloads: 0
piao_tiger 2020-01-21 10:28:19
Description: this is boot file of z turn board
Plat: LINUX | Size: 10073KB | Downloads: 0
sazzad 2020-01-21 03:55:48
Description: IP core for verilog core
Plat: C++ Builder | Size: 668KB | Downloads: 0
amusant 2020-01-20 23:16:07
Description: AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one knows is the open source bus protocol (circumvents all patents). This bridge supports the wishbone B4 version, i.e it supports the use of ready signal, which makes the wishbone a pipelined bus. Wishbone B3 was not pipelined, i.e it can't emit requests unless the previous one has completed. The configurable parameters of this bridge are Address Width, Data Width, Tag Width and the Max_Outstanding_Reqs which sets the pipelinability (how many requests can be in flight) of the bridge. The RTL comes with a home made uvm testbench which I tested on modelsim. Any bug reported w.r.t this uvm testbench will e highly appreciated.
Plat: VHDL | Size: 11KB | Downloads: 0
L_King 2020-01-20 23:04:16
Description: FPGA, 1553B decode, Verilog language
Plat: Verilog | Size: 1KB | Downloads: 0
L_King 2020-01-20 23:02:31
Description: FPGA, 1553B code, Verilog language
Plat: Verilog | Size: 1KB | Downloads: 0
三雨 2020-01-20 03:31:22
Description: Using Verilog to design the 2011 digital circuit competition, about image processing
Plat: Vivado | Size: 1835KB | Downloads: 0
三雨 2020-01-20 03:18:56
Description: Using Verilog language to design the 2016 digital circuit competition, the basic function is high byte input and output
Plat: Vivado | Size: 1925KB | Downloads: 0
hlayumi 2020-01-17 13:47:27
Description: Hslogic algorithm simulation, based on FPGA music generator, can play beautiful music.
Plat: VHDL | Size: 1413KB | Downloads: 1
jonathanhe 2020-01-16 23:33:53
Description: As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.
Plat: C/C++ | Size: 1903KB | Downloads: 0
奔跑蜗牛哥 2020-01-16 16:10:43
Description: VGA data conversion HDMI data, parallel data 24 bit data input, 4-channel oserdes high-speed serial interface output
Plat: Vivado | Size: 11KB | Downloads: 0
ming999 2020-01-14 16:50:15
Description: Different switch states of the DIP switch control the 7-inch LCD screen to display moving 0V, 3.3V, square wave, triangle wave, sine wave or ADC to collect data.
Plat: Verilog | Size: 16607KB | Downloads: 0
ming999 2020-01-14 16:45:25
Description: The ultimate result of ultrasonic ranging shows that every 100ms, a high-pulse excitation of 10us required by an ultrasonic ranging module is generated, and the digitally displayed decimal distance data (unit mm) is displayed in decimal data using a digital tube.
Plat: Verilog | Size: 34754KB | Downloads: 0
ming999 2020-01-14 16:41:57
Description: 5 channels of data + 1 channel of clock for LVDS data transmission and reception, to achieve cyclic transmission of fixed data, LVDS transmission parallel conversion, LVDS reception serial conversion, bit alignment processing and effective data frame analysis.
Plat: Verilog | Size: 21569KB | Downloads: 0
ming999 2020-01-14 16:39:36
Description: This example instantiates the DDR3 controller IP core module provided in Xilinx Vivado to achieve basic DDR3 reader operation. The simulation of the DDR3 IP core is achieved through an example of a test script automatically generated by the IP core.
Plat: Verilog | Size: 48327KB | Downloads: 0
来战何人 2020-01-14 00:02:24
Description: Sequence detection with finite state machine
Plat: Verilog | Size: 2KB | Downloads: 0
wykay 2020-01-13 15:50:18
Description: Xilinx FPGA DMA Driver
Plat: C/C++ | Size: 11289KB | Downloads: 0
小明d1 2020-01-12 21:58:45
Description: The module is used to realize crc_24verification code, output CRC verification success flag, adopt parameterized design, you can modify the parameters to modify the width of input parameters and the number of input data
Plat: Verilog | Size: 1KB | Downloads: 0
jayforgood 2020-01-11 23:42:48
Description: Blink Without Delay Sometimes you need to do two things at once. For example you might want to blink an LED while reading a button press. In this case, you can't use delay(), because Arduino pauses your program during the delay(). If the button is pressed while Arduino is paused waiting for the delay() to pass, your program will miss the button press.
Plat: C/C++ | Size: 15KB | Downloads: 0
王珊儿 2020-01-11 20:42:45
Description: This is a diamond based development environment fpga program, can simulate the heartbeat, flashing lights
Plat: Dev C++ | Size: 2KB | Downloads: 0
王珊儿 2020-01-11 20:41:04
Description: This is an fpga program based on the quarter2 development environment, which can drive seg-led to achieve functions
Plat: Quartus II | Size: 3099KB | Downloads: 0
王珊儿 2020-01-11 20:40:01
Description: This is an fpga program based on the quarter2 development environment
Plat: Quartus II | Size: 3166KB | Downloads: 0
王珊儿 2020-01-11 20:39:03
Description: This is an fpga program based on the quarter2 development environment. Press the button to turn on the light, which can be dimmed according to the pin configuration
Plat: Quartus II | Size: 4494KB | Downloads: 0
王珊儿 2020-01-11 20:34:42
Description: This is a quarter2 based development environment flow lamp program, chip selection is Intel, you can see the schematic diagram change pin configuration
Plat: Quartus II | Size: 6060KB | Downloads: 0
zjohn1998 2020-01-11 17:49:55
Description: The random sequence was written as NRZ sequence, coded as CMI after frequency division, and then decoded as CMI. QuartusII12.0 contains the top-level files and verilog modules
Plat: Verilog | Size: 1710KB | Downloads: 0
poorcool 2020-01-11 15:07:48
Description: Verilog implementation of SD card, including simulation file of modelsim10.6d.
Plat: Verilog | Size: 90KB | Downloads: 0
poorcool 2020-01-11 15:04:24
Description: Verilog implementation of parallel CRC calculation, simulation using modelsim10.6d.
Plat: Verilog | Size: 58KB | Downloads: 0
poorcool 2020-01-11 14:51:42
Description: Verilog implementation of FFT, using butterfly algorithm, including simulation excitation file.
Plat: Verilog | Size: 2604KB | Downloads: 0
sha66666666666666666 2020-01-11 03:58:07
Description: PSO based algorithm for image processing to remove the grey area
Plat: matlab | Size: 3KB | Downloads: 0
TiredBird 2020-01-10 23:31:51
Description: The function generator based on DDS can produce sine wave, square wave, triangle wave and sawtooth wave, in which the frequency and amplitude of all waveforms can be changed, the duty cycle of square wave can be adjusted independently, and these changes can be realized through serial port.
Plat: Verilog | Size: 13KB | Downloads: 0