ITANGTANGI 2020-03-29 22:36:29
Description: Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.
Plat: Verilog | Size: 11045KB | Downloads: 0
zui136 2020-03-29 17:46:12
Description: Verilog read and write LCM1602 program, display on the screen Help on the screen
Plat: C/C++ | Size: 552KB | Downloads: 0
zui136 2020-03-29 17:43:36
Description: Verilog reading and writing PS2 keyboard and mouse.... Hope I love it.
Plat: C/C++ | Size: 1048KB | Downloads: 0
zui136 2020-03-29 17:41:57
Description: SD card reading and writing Verilog version, for some people may be useful.....
Plat: C/C++ | Size: 1160KB | Downloads: 0
张欣宇 2020-03-27 14:40:59
Description: A single cycle CPU is designed, which can realize the basic R-type and J-type instruction function operation.
Plat: Verilog | Size: 4768KB | Downloads: 0
ZDCHXGG 2020-03-26 09:02:57
Description: The reading and writing configuration operation of E2PROM is implemented on FPGA, with simulation model using Modelsim
Plat: Verilog | Size: 6958KB | Downloads: 3
ZDCHXGG 2020-03-26 08:56:55
Description: Using Verilog language to realize the initial configuration of SDRAM and the operation of reading, writing and refreshing, with Modelsim simulation module
Plat: Verilog | Size: 3616KB | Downloads: 2
ZDCHXGG 2020-03-26 08:48:39
Description: Using Verilog language to realize SCCB protocol of interface configuration of camera ov7670
Plat: Verilog | Size: 33KB | Downloads: 2
ZDCHXGG 2020-03-26 08:45:29
Description: On the FPGA board, realize the sending function of the serial port. With the simulation, you need to modify the engineering configuration by yourself
Plat: Verilog | Size: 5286KB | Downloads: 0
ZDCHXGG 2020-03-26 08:40:39
Description: On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation
Plat: Verilog | Size: 13546KB | Downloads: 0
HLhello 2020-03-22 15:50:33
Description: The file realizes the adjustment of pulse width and modulation of pulse width. The change of sound intensity of buzzer is realized by controlling the pulse width
Plat: Verilog | Size: 1KB | Downloads: 0
关键先生Q 2020-03-21 23:36:00
Description: Using Verilog language, NCO, mult and other IP cores are called to realize digital mixing filtering
Plat: Verilog | Size: 9686KB | Downloads: 0
Rachel_Rachel 2020-03-19 14:19:16
Description: Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!
Plat: VHDL | Size: 18804KB | Downloads: 15
jianyunshixi 2020-03-10 22:15:06
Description: Through vivado, the 16 bit running water lamp can flash in order, and the simulation waveform can be displayed
Plat: Vivado | Size: 669KB | Downloads: 0
hexboom 2020-03-01 20:40:57
Description: The FPGA authoritative guide is the most practical essence of FPGA books. The book contains 12 chapters, covering the basic knowledge of FPGA design and the whole process of FPGA design. "FPGA authority guide" is focused and practical, and all the examples listed have been verified.
Plat: Verilog | Size: 2792KB | Downloads: 8
hanshuibi 2020-02-29 15:40:09
Description: Verilog serial port code, including baud rate generation.
Plat: Verilog | Size: 2KB | Downloads: 0
蔺娇娇 2020-02-25 16:10:17
Description: This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.
Plat: Verilog | Size: 19146KB | Downloads: 1
年轻的国王 2020-02-25 11:18:27
Description: FPGA UART test code,simple and easy to study,good
Plat: Verilog | Size: 3447KB | Downloads: 3
年轻的国王 2020-02-25 11:17:02
Description: FPGA pll test code,simple and easy to study,good
Plat: Verilog | Size: 3001KB | Downloads: 0
年轻的国王 2020-02-25 11:15:30
Description: FPGA key test code,simple and easy to study,good
Plat: Verilog | Size: 2923KB | Downloads: 0
小石呀 2020-02-24 16:02:31
Description: Obtain the correlation waveform through multiple rotations
Plat: VHDL | Size: 2KB | Downloads: 1
无线电之家99 2020-02-19 18:16:11
Description: The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn
Plat: Verilog | Size: 5458KB | Downloads: 1
川亓 2020-02-19 15:49:06
Description: The FPGA driver of HC-SR04 is written in Verilog language,which can output the distance (unit: cm).
Plat: Vivado | Size: 29KB | Downloads: 0
南下阳 2020-02-14 17:13:11
Description: In the infrared peripheral experiment, the infrared remote controller is used to send 10 numbers of 0-9 to the development board, and then the development board controls the buzzer to send out different tones according to these 10 different numbers
Plat: Verilog | Size: 4590KB | Downloads: 0
南下阳 2020-02-14 16:58:08
Description: In the PS / 2 peripheral experiment, we use the PS / 2 keyboard to send 10 numbers of 0-9 to our development board, and then the development board controls the buzzer to send out different tones according to these 10 different numbers.
Plat: Verilog | Size: 3194KB | Downloads: 0
南下阳 2020-02-14 16:51:37
Description: In the experiment of multi terminal song ordering system, we can use the serial peripheral to send 0-9 10 digital control buzzers to send different tones, use the PS / 2 peripheral to send 0-9 10 digital control buzzers to send different tones, and use the infrared peripheral to send 0-9 10 digital control buzzers to send different tones.
Plat: Verilog | Size: 3793KB | Downloads: 0
bkt340 2020-02-14 13:25:24
Description: A FSM for lights of a car while taking right or left turn working on zedboard .
Plat: Verilog | Size: 32KB | Downloads: 0
bkt340 2020-02-14 13:22:30
Description: A working counter written in verilog code .
Plat: Verilog | Size: 33KB | Downloads: 0
flyingLee 2020-02-10 09:49:11
Description: The soft core realizes hmdi video stream encoding and decoding, supports multiplex output and Axi bus
Plat: Verilog | Size: 1963KB | Downloads: 3
ati7 2020-02-03 15:47:57
Description: verilog code for digital system design task5
Plat: Verilog | Size: 298KB | Downloads: 0