shukeihei 2019-11-13 19:56:51
Description: Sampling test for ADC
Plat: Others | Size: 2KB | Downloads: 0
zongc 2019-11-11 21:14:30
Description: Clock division using Verilog
Plat: Verilog | Size: 511KB | Downloads: 0
sayaca 2019-11-10 21:02:47
Description: DES algorithm implemented in verilog.
Plat: Verilog | Size: 2478KB | Downloads: 0
兴鹏 2019-10-30 11:39:44
Description: Verilog implementation of a median filtering algorithm
Plat: Verilog | Size: 4KB | Downloads: 1
hxq160 2019-10-28 13:35:43
Description: nice verilog course,try to download, wish it help you
Plat: Verilog | Size: 4737KB | Downloads: 2
Groupies 2019-10-28 13:32:15
Description: Verilog is more suitable for algorithm level, register transfer level, logic level, gate level and design.
Plat: Quartus II | Size: 844KB | Downloads: 0
Groupies 2019-10-28 13:11:12
Description: In this paper, Verilog HDL hardware description language is introduced to introduce the relationship between signal processing and hardware logic design, as well as the related basic concepts.
Plat: Verilog | Size: 1323KB | Downloads: 0
李文也 2019-10-27 15:20:45
Description: The 17 level pipeline CORDIC algorithm can be used to calculate the sine and cosine values of the angle in the circular coordinate system
Plat: VHDL | Size: 2KB | Downloads: 0
里呼呼呼 2019-10-25 16:25:03
Description: This is a very suitable book for beginners to learn how to use Verilog. It is also a classic book.
Plat: Verilog | Size: 6978KB | Downloads: 0
ReRaugCrux 2019-10-24 17:00:46
Description: I2C - communication protocol design imlementation using verilog HDL.
Plat: Verilog | Size: 186KB | Downloads: 0
liulang128 2019-10-24 10:02:59
Description: Realization and Simulation of four bit adder
Plat: Verilog | Size: 2KB | Downloads: 0
ChasenDong 2019-10-17 20:21:40
Description: EEPROM read and write routine, IIC communication program iic_com.v, top level file eeprom_test.v
Plat: Verilog | Size: 2KB | Downloads: 0
ChasenDong 2019-10-17 19:54:04
Description: Serial port Uart communication routine, receiving program design, Uart receiving program contains three programs, respectively, clock generation program clkdiv.v, serial port sending program uarttx.v and serial port receiving test program.
Plat: Verilog | Size: 1KB | Downloads: 0
ChasenDong 2019-10-17 19:51:33
Description: Serial port Uart communication routine, send program design, Uart send program contains three programs, respectively is the clock generation program clkdiv.v, serial port send program uarttx.v and serial port send test program.
Plat: Verilog | Size: 2KB | Downloads: 0
ChasenDong 2019-10-17 19:45:32
Description: Key detection process, when pressed the key corresponding light will be on, press again, the light will be off, cycle and repeat
Plat: Verilog | Size: 1KB | Downloads: 0
joris30 2019-10-16 11:26:20
Description: Realize multi clock FIFO with overflow protection
Plat: Verilog | Size: 1KB | Downloads: 1
rehman684 2019-10-14 05:18:04
Description: and gate using verilog
Plat: Verilog | Size: 26KB | Downloads: 0