knkbancon 2019-12-05 23:59:14
Description: Quartus best tooollll
Plat: Quartus II | Size: 481KB | Downloads: 0
Jank1 2019-12-05 19:08:04
Description: File testing, please download carefully, if there is a problem, please advise, do not spray.
Plat: Verilog | Size: 3KB | Downloads: 0
在角落里 2019-11-23 21:22:38
Description: requency division; frequency demultiplication; dividing frequency; scaling-down
Plat: VHDL | Size: 9KB | Downloads: 0
可儿99 2019-11-19 17:09:00
Description: Using CPLD device and experimental development board, a controller of the range hood is designed and implemented.
Plat: Verilog | Size: 6847KB | Downloads: 0
帅帅的凯 2019-11-16 18:52:34
Description: Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.
Plat: VHDL | Size: 351KB | Downloads: 0
neoskr 2019-06-13 08:40:16
Description: The Test about Computer Science
Plat: C/C++ | Size: 42988KB | Downloads: 0
EOF 2019-05-26 18:52:54
Description: FPGA interface for ADI AD9369 quad high speed ADC, Altera Quartus project and Verilog source code included
Plat: Verilog | Size: 581KB | Downloads: 9
asdfgg 2019-05-14 11:10:35
Description: Datasheet.Beginners quatusII good helper, recommended to download the study
Plat: Quartus II | Size: 1098KB | Downloads: 0
3wnj9u3 2019-05-12 02:53:41
Description: Quartus 18.0 for Linux
Plat: LINUX | Size: 19333KB | Downloads: 9
3wnj9u3 2019-05-12 02:52:33
Description: Quartus Prime 17.0 for Linux
Plat: LINUX | Size: 9961KB | Downloads: 3
kiski 2019-05-03 00:58:10
Description: quartus ckrack for windows users
Plat: Windows_Unix | Size: 823KB | Downloads: 0
hanziG 2019-05-02 09:01:12
Description: The basic gate circuits, and gates, non-gates, exclusive or gates, and non-gates, or gates, and non-gates can be implemented in a case-by-case manner.
Plat: VHDL | Size: 23400KB | Downloads: 0
Vlad13 2019-05-02 04:24:30
Description: Working VHDL code for amplifier LTC6912, adc LTC1407A-1, dac LTC2624. Archive includes vhdl files and ucf file with comments. Create new project add files and it will be to work.
Plat: MQL | Size: 13320KB | Downloads: 1
cmgeolo 2019-04-25 01:36:19
Description: Quartus 61 datalogger firmware
Plat: WINDOWS | Size: 55159KB | Downloads: 0
ada1s2h 2019-03-30 12:22:59
Description: quartus crack full ver
Plat: WINDOWS | Size: 423KB | Downloads: 1
麒零丿空 2019-03-25 21:36:33
Description: Upper board file enlarged by OV7670 camera module image for reference only
Plat: Quartus II | Size: 25846KB | Downloads: 0
yem 2019-03-07 16:08:17
Description: risc processor vhdl code 32 bit
Plat: VHDL | Size: 252KB | Downloads: 0
yem 2019-03-07 16:06:14
Description: sayeh processor vhdl
Plat: VHDL | Size: 2823KB | Downloads: 0
yem 2019-03-07 16:03:20
Description: VHDL FOR 32 BIT MIPS
Plat: VHDL | Size: 730KB | Downloads: 0
h2hermit 2019-02-24 17:32:38
Description: quartus The solution of the Electronic Design Competition in the past years The solution of the Electronic Design Competition in the past years
Plat: C/C++ | Size: 442KB | Downloads: 10
sianewww 2019-01-25 16:31:44
Description: Designing a 6-Divider with 50% duty cycle
Plat: Quartus II | Size: 277KB | Downloads: 0
思66 2019-01-10 17:48:42
Description: Quartus II programming software, support verilog, schematic diagram and other programming methods
Plat: Quartus II | Size: 1417KB | Downloads: 1
Groomwall 2019-01-03 08:01:42
Description: Ghfhfhwj djwjdw a a edjwdiiidi iidwi idwidi wiidiwd id widiwidiwd. Dwididiiwdididwidi d wdd das wai wol do d dwddwdwdw.
Plat: HTML | Size: 2192KB | Downloads: 0
Teng Teng 2018-12-21 12:30:03
Description: Traffic lights made by quartus software and Verilog are realized in the form of state machine
Plat: C/C++ | Size: 614KB | Downloads: 2
hkx888 2018-12-16 14:14:31
Description: It can be used to read and play ram directly on quartus
Plat: Quartus II | Size: 1029KB | Downloads: 0
懒懒666 2018-12-15 22:54:42
Description: PLL phase-locked loop generated by macro module in Quartus II 13.1
Plat: Quartus II | Size: 167KB | Downloads: 1