yingjp 2019-07-22 15:47:04
Description: Xilinx's official virtex-6 user manual for FPGA chips
Plat: PDF | Size: 9432KB | Downloads: 0
xsac 2019-07-17 16:12:31
Description: The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.
Plat: Verilog | Size: 583KB | Downloads: 1
xsac 2019-07-17 16:10:35
Description: Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module
Plat: Verilog | Size: 498KB | Downloads: 1
xsac 2019-07-17 16:08:16
Description: A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.
Plat: VHDL | Size: 701KB | Downloads: 1
xsac 2019-07-17 16:05:26
Description: This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay
Plat: VHDL | Size: 644KB | Downloads: 1
xsac 2019-07-17 15:59:52
Description: The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.
Plat: VHDL | Size: 543KB | Downloads: 1
omidjoon 2019-07-16 01:12:48
Description: LitePCIe provides a small footprint and configurable PCIe core. LitePCIe is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... Using Migen to describe the HDL allows the core to be highly and easily configurable. LitePCIe can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.
Plat: Python | Size: 488KB | Downloads: 1
omidjoon 2019-07-16 01:05:24
Description: SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.
Plat: Verilog | Size: 85KB | Downloads: 1
DN-User-09 2019-07-15 07:48:51
Description: Xilinx Licenses 2018
Plat: WINDOWS | Size: 11KB | Downloads: 2
sdersder 2019-06-18 08:29:28
Description: This is the most basic routine for getting started with GTH high-speed transceivers. The internal ibert test is configured with 24 channels, each channel has a rate of 10Gb/s and the reference clock is 125M, whether it is the normal transceiver mode or the loopback loopback mode. After 24 hours of testing, the bit error rate has been 0.
Plat: VHDL | Size: 13658KB | Downloads: 3
pokapone 2019-06-09 22:06:31
Description: xilinx rs232 serial to parralel interface
Plat: VHDL | Size: 201KB | Downloads: 0
pokapone 2019-06-09 22:01:41
Description: xilinx serial to parralel interface
Plat: VHDL | Size: 332KB | Downloads: 0
Lsjt 2019-06-06 09:44:36
Description: Zcu111 board card ibert manual, detailed introduction of ibert project establishment and configuration method.
Plat: Others | Size: 5779KB | Downloads: 0
Exooo 2019-05-30 19:15:28
Description: Xilinx meeting Slide
Plat: Verilog | Size: 40777KB | Downloads: 0
fxy212127 2019-05-11 16:18:29
Description: xilinx guide for the new user
Plat: VHDL | Size: 636KB | Downloads: 1
Reborn_Lee 2019-05-10 10:45:27
Description: This is a sequence detector project file, written with Verilog, detection sequence 101, code style is good, it is worth downloading.
Plat: Vivado | Size: 63KB | Downloads: 0
yuyangfei 2019-05-09 08:14:14
Description: Xilinx USB driver for win10, newer version
Plat: Vivado | Size: 459KB | Downloads: 2
snappi 2019-05-07 04:40:06
Description: Arty Z7 20 HDMI output
Plat: WINDOWS | Size: 22706KB | Downloads: 0
lynnsp 2019-03-11 13:11:22
Description: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT
Plat: C++ | Size: 37130KB | Downloads: 0
manuvvasuv 2019-03-05 19:27:57
Description: verilog code for LFSR design
Plat: Verilog | Size: 115KB | Downloads: 0
manuvvasuv 2019-03-05 19:27:21
Description: verilog code for encoder with priority
Plat: Verilog | Size: 109KB | Downloads: 0
manuvvasuv 2019-03-05 19:26:38
Description: verilog code for BCD subtractor
Plat: Verilog | Size: 120KB | Downloads: 0
manuvvasuv 2019-03-05 19:26:04
Description: verilog code for BCD adder
Plat: Verilog | Size: 118KB | Downloads: 0
manuvvasuv 2019-03-05 19:25:19
Description: verilog code for arbitrary counter
Plat: Verilog | Size: 115KB | Downloads: 0
manuvvasuv 2019-03-05 19:22:59
Description: Verilog codes for the LFSR design
Plat: Verilog | Size: 579KB | Downloads: 0
Alexwei 2019-02-23 02:04:38
Description: Code to do easy Binary to Dec. Plug and play
Plat: VHDL | Size: 788KB | Downloads: 0