SHAL7 2020-02-11 22:09:15
Description: vhdl code for i2c rx cpld zip file
Plat: VHDL | Size: 11KB | Downloads: 0
荏苒88 2019-12-10 10:09:15
Description: The signal for multiple input and one output is selected in CPLD
Plat: VHDL | Size: 204KB | Downloads: 0
哎呀我去603 2019-11-18 19:54:00
Description: Short circuit fault protection of three-phase inverter to prevent through phenomenon caused by opening and closing delay during open circuit fault test
Plat: VHDL | Size: 189KB | Downloads: 0
方式分散 2019-11-07 10:47:01
Description: CPLD decoding code fslkgflkds
Plat: VHDL | Size: 4KB | Downloads: 0
zhua 2019-04-24 08:03:16
Description: CPLD learning materials, CPLD basic routines, for beginners and programming reference is very helpful.
Plat: Verilog | Size: 7102KB | Downloads: 0
hirameki 2019-04-13 07:46:10
Description: example code for EPM240 dev board
Plat: VHDL | Size: 214KB | Downloads: 0
yiyisunshine 2018-12-10 15:00:33
Description: communicate with MCU and protection
Plat: VHDL | Size: 859KB | Downloads: 1
木子君晨 2018-12-10 10:32:33
Description: Motor Control Fault Protection Based on CPLD EMP240
Plat: VHDL | Size: 297KB | Downloads: 2
Miffy晨光 2018-10-08 09:36:51
Description: SRAM read / write test experiment
Plat: Verilog | Size: 1KB | Downloads: 0
lijianrong_1997 2018-09-14 16:07:04
Description: The serial port function can be realized in FPGA or CPLD, and the parallel port operation can be realized by the processor.
Plat: VHDL | Size: 1KB | Downloads: 1
majinzhu 2018-08-23 09:31:54
Description: FPGA beginners tutorial and reference learning code, I hope to help beginners.
Plat: VHDL | Size: 2718KB | Downloads: 2
非欧 2018-08-20 14:11:24
Description: VHDL language and CPLD development
Plat: VHDL | Size: 775KB | Downloads: 0
nooru 2018-07-07 11:54:24
Description: Software for burning Xilinx bit files
Plat: Verilog | Size: 1757KB | Downloads: 2
lyy521 2018-06-19 16:10:54
Description: MAIIEPM240T100I5N's example program, which has been running on the development board, can communicate with the SPI and CPU, has two ways to control the step motor's PWM Road, and 16 IO ports are written as trace functions (installing the corresponding sensors can be used for trace).
Plat: VHDL | Size: 1151KB | Downloads: 1
sven-luo 2018-06-15 15:04:01
Description: LED control code,Verilog ,CPLD
Plat: Verilog | Size: 3KB | Downloads: 0
lisihao 2018-05-23 18:12:09
Description: Example navigation of typical module design of 51 single chip microcomputer
Plat: C/C++ | Size: 3847KB | Downloads: 0
yymj 2018-04-22 14:53:04
Description: drive CCD 1705 from Toshiba
Plat: Quartus II | Size: 462KB | Downloads: 2
小竹丶 2018-03-24 15:12:14
Description: This system is a CPLD microcontroller for signal frequency and period, time interval and the duty ratio of digital frequency measurement meter based on the system by the AGC (automatic gain control) circuit, amplifier circuit, high speed broadband comparison circuit to achieve effective value of 10mV/ 100MHz and the frequency of processing components, including AGC circuit control signal after amplification is consistent within a certain range of amplitude automatic gain circuit compares the former circuit output signal is converted into CPLD, using precision frequency measurement principle, realizes high accuracy time gate 1S. SCM communication processing data and display, data show that the system precision to play a part of the requirements.
Plat: VHDL | Size: 76KB | Downloads: 5
Jerry20170718 2018-03-21 10:05:07
Description: Learn CPLD and VERILOG HDL from zero
Plat: VHDL | Size: 32207KB | Downloads: 7
哈哈凸 2018-02-12 17:00:38
Description: Based on the ALTERA FPGA design guidance data, very good advanced data, primary FPGA engineers go to the senior engineering teachers' ethics must read books.
Plat: WINDOWS | Size: 45736KB | Downloads: 7
hurui 2018-01-09 08:53:14
Description: Five level SVPWM pulse trigger program based on CPLD hardware description language
Plat: Quartus II | Size: 327KB | Downloads: 11
w74177 2018-01-03 14:37:38
Description: Control ADC0804 verilog code, cpld / fpga can be used to display the ADC digital tube with the binary data collected.
Plat: Verilog | Size: 1KB | Downloads: 5
ByrPx 2017-12-18 16:19:45
Description: The function that can be used to achieve a birthday card
Plat: Verilog | Size: 1208KB | Downloads: 15
林云峰 2017-12-06 19:30:50
Description: Realization of synchronization vector acquisition program based on clock signal, based on CPLD and stm32f407
Plat: C/C++ | Size: 18224KB | Downloads: 3
Farook 2017-11-16 14:13:59
Description: SPI Implementation on CPLD
Plat: Verilog | Size: 3135KB | Downloads: 1
jkyguhg 2017-11-02 20:35:01
Description: CPLD program development based on PAC1220 program
Plat: Verilog | Size: 964KB | Downloads: 1
帅哥1111 2017-10-23 09:03:34
Description: Calendar written by VHDL
Plat: VHDL | Size: 819KB | Downloads: 3
Quinn chen 2017-08-02 23:38:43
Description: 51 MCU and CPLD two-way serial transceiver,Requires hardware support and this version is successfully debugged on the actual hardware
Plat: C/C++ | Size: 21620KB | Downloads: 1
Hauser.Z 2017-08-02 21:13:17
Description: can improve the application of fpga
Plat: VHDL | Size: 92527KB | Downloads: 4
lijunpeng0390 2017-08-02 18:47:48
Description: CPLD introduction, please look carefully, very basic, you can print out
Plat: Visual C++ | Size: 136KB | Downloads: 1