mn7928 2017-12-14 22:42:10
Description: u should upload 5 codes/documents
Plat: WINDOWS | Size: 24KB | Downloads: 0
echangjiang 2017-12-14 15:53:01
Description: To eliminate the jitter of the key in the FPGA, the fall prevention and other parts
Plat: Verilog | Size: 1KB | Downloads: 0
echangjiang 2017-12-14 15:46:27
Description: SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;
Plat: Vivado | Size: 2520KB | Downloads: 0
刘同学 2017-12-14 11:11:32
Description: ddr3 controller, can be used to ddr3 control,high speed
Plat: Verilog | Size: 33KB | Downloads: 1
2017-12-14 09:10:59
Description: costing system of network
Plat: WINDOWS | Size: 3KB | Downloads: 0
stas 2017-12-13 21:46:16
Description: SPI master slave (fpga/verilog)
Plat: Verilog | Size: 66KB | Downloads: 0
stas 2017-12-13 21:44:22
Description: SPI controller (fpga/verilog)
Plat: Verilog | Size: 117KB | Downloads: 0
stas 2017-12-13 21:42:35
Description: Round Robin priority arbiter
Plat: Verilog | Size: 46KB | Downloads: 0
stas 2017-12-13 21:38:47
Description: 2 master - 2 slave communication crossbar
Plat: Verilog | Size: 15KB | Downloads: 0
任印印 2017-12-13 18:14:55
Description: CY7C68013 firmware program FPGA test Verilog program, source code
Plat: Verilog | Size: 194KB | Downloads: 0
hyh 2017-12-13 18:14:13
Description: AMBA bus IP Verilog code
Plat: LINUX | Size: 78KB | Downloads: 0
邓奇 2017-12-13 16:20:44
Description: Bird board game on the development board EGO1, a detailed module description, the use of vivdao platform
Plat: Verilog | Size: 510KB | Downloads: 0
高文旭 2017-12-11 16:09:36
Description: Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.
Plat: Vivado | Size: 623KB | Downloads: 2
逍貂莫 2017-12-11 14:43:36
Description: Digital system design and the fourth edition of Verilog Wang Jinming The sixth chapter after class exercise reference analysis
Plat: Quartus II | Size: 4058KB | Downloads: 0
JIN 2017-12-11 11:41:07
Description: Using the Verilog language to write key anti - chattering code and verify it by modlesim
Plat: Verilog | Size: 3165KB | Downloads: 4
JIN 2017-12-11 11:29:46
Description: The CRC16 check code based on Quartus II and the realization of the simulation verification by Modlsim
Plat: Verilog | Size: 48914KB | Downloads: 0
JIN 2017-12-11 11:18:20
Description: Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conversion between binary and gray code
Plat: Verilog | Size: 2908KB | Downloads: 0
黄卓仪 2017-12-11 10:47:46
Description: JK flip-flop description of Verilog
Plat: WINDOWS | Size: 5KB | Downloads: 1
王胜霞 2017-12-11 09:46:49
Description: In the process of VCs cracking, a tutorial on the specific generation of license.
Plat: LINUX | Size: 106KB | Downloads: 1
浩林 2017-12-11 09:19:33
Description: The implementation of divider, alu, ram etc. in verilog
Plat: Verilog | Size: 7KB | Downloads: 1
佳豪森 2017-12-11 08:27:15
Description: Very useful basic module full set download
Plat: Vivado | Size: 1KB | Downloads: 0
mohammadreza 2017-12-10 19:12:53
Description: gladoyator subtitle in verilog!!
Plat: Verilog | Size: 30KB | Downloads: 0
mohammadreza 2017-12-10 19:12:03
Description: friends full pack subtitle in verilog!!
Plat: Verilog | Size: 301KB | Downloads: 0
mohammadreza 2017-12-10 19:11:08
Description: state jones sub nevis in verilog
Plat: Verilog | Size: 38KB | Downloads: 0
mohammadreza 2017-12-10 19:09:21
Description: fight club zirnevis in verilog
Plat: Verilog | Size: 64KB | Downloads: 0
mohammadreza 2017-12-10 19:08:35
Description: sub down subtitle in verilog
Plat: Verilog | Size: 14KB | Downloads: 0
padma priyanka 2017-12-10 14:54:46
Description: lp scan architecture
Plat: VHDL | Size: 3497KB | Downloads: 0
Arwen yuan 2017-12-09 17:51:15
Description: Verilog language introductory course, detailing the Verilog syntax and Application
Plat: Verilog | Size: 3019KB | Downloads: 0
2017-12-09 10:09:50
Description: Serial communication and serial communication with Verilog based on Quartus
Plat: Quartus II | Size: 11019KB | Downloads: 1
杨凯 2017-12-08 17:56:02
Description: The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code
Plat: VHDL | Size: 500KB | Downloads: 1