idsoft 2018-05-20 19:54:43
Description: LED Verilog test, to test the FPGA using Verilog code on the altera FPGA board.
Plat: Verilog | Size: 2931KB | Downloads: 0
laraib 2018-05-20 15:19:47
Description: full subtractor in verilog
Plat: Verilog | Size: 515KB | Downloads: 0
laraib 2018-05-20 15:16:01
Description: 16bit priority encoder
Plat: Verilog | Size: 554KB | Downloads: 0
laraib 2018-05-20 14:59:12
Description: full adder using half adder instance
Plat: Verilog | Size: 517KB | Downloads: 0
laraib 2018-05-20 14:56:14
Description: multiplexer 8x1 through instantiation
Plat: Verilog | Size: 529KB | Downloads: 0
asde198250 2018-05-20 10:20:28
Description: Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.
Plat: VHDL | Size: 1439KB | Downloads: 0
空气蛹 2018-05-17 23:05:19
Description: Contains three source code and test files, one is the frequency meter, one is the FIR filter, the other is the Barker code sequence detector.
Plat: VHDL | Size: 4KB | Downloads: 0
Hon123 2018-05-17 17:52:05
Description: Two select a multi path selector, including program code, including simulation waveform.
Plat: Verilog | Size: 109KB | Downloads: 0
yangxuchen 2018-05-17 11:53:11
Description: Verilog based DDS implementation, can achieve sine wave, triangle wave and sawtooth wave, based on ISE14.7
Plat: Verilog | Size: 17892KB | Downloads: 0
youshuai423 2018-05-17 09:42:46
Description: A rising edge delay program is written for FPGA of Altera company. It can generate dead time for PWM control and prevent simultaneous conduction breakdown of upper and lower transistors.
Plat: Verilog | Size: 4892KB | Downloads: 0
lunaticlili 2018-05-17 09:17:34
Description: Through the serial debugging program input string, enter the FPGA development board, through the VGA display on the LCD screen.
Plat: VHDL | Size: 4575KB | Downloads: 0
youshuai423 2018-05-17 09:05:41
Description: The number of 1-9 is transmitted from outside to FPGA, which is displayed by digital LED after processing.
Plat: Verilog | Size: 3101KB | Downloads: 0
byronlee 2018-05-17 02:57:39
Description: It's easy for the beginner who wants to study verilog hdl language.
Plat: Verilog | Size: 13146KB | Downloads: 0
小白龙008 2018-05-16 21:10:56
Description: Verilog design buck code circuit, and use Modesim simulation, FPGA synthesis.
Plat: VHDL | Size: 4173KB | Downloads: 2
小白龙008 2018-05-16 21:05:35
Description: Verilog design buck code circuit, and use Modesim simulation, FPGA synthesis.
Plat: VHDL | Size: 4606KB | Downloads: 0
liang643 2018-05-16 15:25:37
Description: Verilog implementation of five level pipelined CPU design
Plat: Verilog | Size: 28KB | Downloads: 0
ranaihtsham 2018-05-16 11:02:45
Description: These are verilog operators.
Plat: VHDL | Size: 50KB | Downloads: 0
WORLD_QU 2018-05-15 20:46:50
Description: Using a 1HZ clock as a reference signal, a frequency of 10 Hz to 10 MHz is measured. In the circuit, eight cascaded modulo 10 counters are used for counting, and 8 modulo 10 counters output 8421 BCD codes of the first to eighth bits, respectively.
Plat: Verilog | Size: 1KB | Downloads: 0
spinz 2018-05-15 20:10:51
Description: FPGA digital clock based on Verilog and built by ISE
Plat: Verilog | Size: 795KB | Downloads: 0
雾雨Kirisame 2018-05-15 13:51:56
Description: The electronic stopwatch is implemented, based on the Xilinx development board.
Plat: VHDL | Size: 2KB | Downloads: 0
vokeal 2018-05-14 10:00:46
Description: Serial lock by password, implemented by state automaton.
Plat: Verilog | Size: 217KB | Downloads: 0
dhjimr 2018-05-13 08:22:25
Description: verilog code for manage camera fpga
Plat: Verilog | Size: 2159KB | Downloads: 2
DanZH 2018-05-12 20:23:27
Description: ece5881lab1011codes full version
Plat: Verilog | Size: 24KB | Downloads: 0
wulihz 2018-05-12 18:00:47
Description: Contains 8 bits of water lamp, module 200 counter and circular display 0~8 digital tube, suitable for beginners to use.
Plat: Quartus II | Size: 11KB | Downloads: 0
haixiaolan 2018-05-11 09:55:21
Description: Verilog language is used to implement a 8*8 multiplier, which is simple in structure and concise in language.
Plat: Verilog | Size: 29KB | Downloads: 0
vict0r 2018-05-11 09:21:32
Description: OV5640's VGA display program, Verilog language
Plat: Quartus II | Size: 12KB | Downloads: 8
qq123233 2018-05-11 00:49:58
Description: Several Verilog routines include registers, latches, triggers, and so on.
Plat: Verilog | Size: 2812KB | Downloads: 0
qq123233 2018-05-11 00:45:04
Description: 999 counter, S8 has S1 reset function, FPGA verification.
Plat: Verilog | Size: 10695KB | Downloads: 0
qq123233 2018-05-11 00:42:04
Description: The 7 LED lights show that you can modify the number and location of your own display. To be successful in simulation
Plat: Verilog | Size: 25KB | Downloads: 0