stas 2017-12-13 21:46:16
Description: SPI master slave (fpga/verilog)
Plat: Verilog | Size: 66KB | Downloads: 0
季寒 2017-12-13 21:45:44
Description: In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.
Plat: PDF | Size: 2433KB | Downloads: 0
stas 2017-12-13 21:44:22
Description: SPI controller (fpga/verilog)
Plat: Verilog | Size: 117KB | Downloads: 0
季寒 2017-12-13 21:43:38
Description: The method of using IP core in FPGA is described.
Plat: PDF | Size: 3007KB | Downloads: 0
stas 2017-12-13 21:42:35
Description: Round Robin priority arbiter
Plat: Verilog | Size: 46KB | Downloads: 0
stas 2017-12-13 21:38:47
Description: 2 master - 2 slave communication crossbar
Plat: Verilog | Size: 15KB | Downloads: 0
邓奇 2017-12-13 16:20:44
Description: Bird board game on the development board EGO1, a detailed module description, the use of vivdao platform
Plat: Verilog | Size: 510KB | Downloads: 0
wang 2017-12-12 22:26:01
Description: Cyclone V development board implements digital stopwatch function, with start, pause, reset function. It can be shown hours, minutes, seconds.
Plat: Quartus II | Size: 8053KB | Downloads: 0
wang 2017-12-12 22:24:02
Description: CYCLONE V control the control of LED lamp
Plat: Quartus II | Size: 7240KB | Downloads: 0
wang 2017-12-12 22:21:45
Description: Cyclone V development of experimental board to realize 8 bit flow lamp of FPGA
Plat: Quartus II | Size: 4283KB | Downloads: 0
毛戌宁 2017-12-12 16:30:52
Description: FPGA design strategy and process, including time series convergence and pin constraints
Plat: Verilog | Size: 10168KB | Downloads: 0
ruusl 2017-12-12 04:32:34
Description: regregwergerw gewrgewrgewr gergewrgewrgrew
Plat: Visual C++ | Size: 25KB | Downloads: 0
一凡 2017-12-11 22:12:51
Description: ADC Analog-to-Digital, the abbreviation of Converter fingerprint / digital converter or analog / digital converter. A device that converts the analog signal of a continuous variable into a discrete digital signal. Analog signals in the real world, such as temperature, pressure, sound, or images, need to be converted into more easily stored, processed and transmitted digital forms. The analog / digital converter can achieve this function, and it can be found in a variety of products.
Plat: VHDL | Size: 79198KB | Downloads: 0
陈盛林 2017-12-11 21:03:50
Description: Example of digital tube simulation
Plat: WINDOWS | Size: 4183KB | Downloads: 0
飞飞飞 2017-12-11 19:31:51
Description: It is used for sampling and displaying the current and voltage of NI single-chip microcomputer. It contains part of program-controlled current and program-controlled voltage and can be used for parallel current-limiting and voltage-limiting circuit.
Plat: C-C++ | Size: 3KB | Downloads: 0
张硕 2017-12-11 14:34:00
Description: Realizing data transmission of PCI
Plat: Quartus II | Size: 541KB | Downloads: 1
JIN 2017-12-11 11:41:07
Description: Using the Verilog language to write key anti - chattering code and verify it by modlesim
Plat: Verilog | Size: 3165KB | Downloads: 4
JIN 2017-12-11 11:29:46
Description: The CRC16 check code based on Quartus II and the realization of the simulation verification by Modlsim
Plat: Verilog | Size: 48914KB | Downloads: 0
JIN 2017-12-11 11:18:20
Description: Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conversion between binary and gray code
Plat: Verilog | Size: 2908KB | Downloads: 0
浩林 2017-12-11 09:19:33
Description: The implementation of divider, alu, ram etc. in verilog
Plat: Verilog | Size: 7KB | Downloads: 1
xhimi 2017-12-10 19:58:37
Description: A weather station is a facility, either on land or sea, with instruments and equipment for measuring atmospheric conditions to provide information for weather forecasts and to study the weather and climate. The measurements taken include temperature, atmospheric pressure, humidity, wind speed, wind direction
Plat: VHDL | Size: 1908KB | Downloads: 0
ZGQ 2017-12-09 20:56:58
Description: Key elimination jitter based on FPGA function implementation
Plat: VHDL | Size: 3073KB | Downloads: 0
zhangwei 2017-12-09 13:50:26
Description: ug906-vivado-design-analysis
Plat: Verilog | Size: 1663KB | Downloads: 0
2017-12-09 10:09:50
Description: Serial communication and serial communication with Verilog based on Quartus
Plat: Quartus II | Size: 11019KB | Downloads: 1
Cao Thanh Hai 2017-12-09 01:00:18
Description: Horizontal size of Unix machines. The latest name of the AS400 is the IBM Iseries (I = Integrated), which is integrated because it is sold with all the pre-installed programs. The AS400 is aimed at mid-market companies, with few technical teams to manage.
Plat: Asm | Size: 1137KB | Downloads: 0
wangna 2017-12-08 17:22:34
Description: Control system of elevator operation
Plat: Verilog | Size: 1KB | Downloads: 1
李燕 2017-12-08 13:37:33
Description: The steering control of the car traffic taillight is realized by using the VHDL language.
Plat: C-C++ | Size: 41064KB | Downloads: 0
巩奕 2017-12-08 08:09:39
Description: To realize taxi billing function, it can show mileage and cost
Plat: VHDL | Size: 13483KB | Downloads: 1
李显龙 2017-12-07 17:08:04
Description: FPGA Verilog Code for TLC549 Caluc ADC Value
Plat: WINDOWS | Size: 2KB | Downloads: 0
孙天人 2017-12-06 20:04:00
Description: The UART experiment program you write can select the baud rate 2400/4800/9600/19200 by key and display the current baud rate through the digital tube. Each press key is sent to a frame of data, and the data is sent through two bit digital tubes. For novice.
Plat: Quartus II | Size: 6600KB | Downloads: 0