董然 2017-10-20 19:39:42
Description: SDRAM read and write function by verilog
Plat: Verilog | Size: 644KB | Downloads: 0
罗荡慰 2017-10-19 00:15:10
Description: Can achieve a modulation method of ASK, the language is Verilog
Plat: Quartus II | Size: 10KB | Downloads: 0
罗荡慰 2017-10-19 00:10:17
Description: Program to achieve a FSK demodulation, the language is verilog.
Plat: Quartus II | Size: 14142KB | Downloads: 0
罗荡慰 2017-10-19 00:08:22
Description: Program to achieve a FSK modulation, the language is verilog.
Plat: Quartus II | Size: 644KB | Downloads: 0
罗荡慰 2017-10-19 00:06:16
Description: One can achieve MSK demodulation, the language is Verilog
Plat: Quartus II | Size: 8442KB | Downloads: 0
罗荡慰 2017-10-18 23:58:10
Description: MSK demodulation can be achieved, and the language is Verilog.
Plat: Quartus II | Size: 21315KB | Downloads: 0
aasdddsa 2017-10-17 03:04:08
Description: turbo c writing, and random fireworks animation, size, color, make their own adjustments. the the
Plat: WINDOWS | Size: 2KB | Downloads: 0
Dharm 2017-10-16 18:02:44
Description: Theory, vol. 49, pp. 937-950, Apr. 2003.
Plat: LINUX | Size: 720KB | Downloads: 0
yang tack 2017-10-16 09:34:09
Description: Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-1200HC-4TG144CR1, and make the simple path diagram on the demo board
Plat: Verilog | Size: 3089KB | Downloads: 0
夏云 2017-10-15 20:25:10
Description: Some of the more practical source code for beginners
Plat: Verilog | Size: 1251KB | Downloads: 4
王月 2017-10-13 09:46:04
Description: Various common interfaces based on FPGA
Plat: WINDOWS | Size: 350KB | Downloads: 0
zhangjianqiang 2017-10-12 14:41:07
Description: Altera FPGA design serial communication, serial assistant to achieve the number of control circuit board, small lights out
Plat: Quartus II | Size: 3338KB | Downloads: 0
席利根 2017-10-11 15:50:56
Description: Through the PS2 port to achieve the keyboard link, the FPGA input.
Plat: Verilog | Size: 679KB | Downloads: 0
喵总 2017-10-11 13:40:10
Description: This is a counter that can be recorded to 60, and can be used for the hierarchical design of digital clock.
Plat: Quartus II | Size: 3003KB | Downloads: 0
韦福 2017-10-11 10:47:26
Description: Use FPGA to read SD card audio playback
Plat: VHDL | Size: 4KB | Downloads: 0
黄绪威 2017-10-11 10:03:02
Description: xilinx spant6 PLL frequency division
Plat: WINDOWS | Size: 1587KB | Downloads: 0
姜勇宏 2017-10-10 14:47:16
Description: (1) coins and paper notes can be entered. The range of coin recognition is 5 cents and 1 yuan coins. The range of identification of notes is 1 yuan, 5 yuan, 10 yuan, 20 yuan, 50 yuan, 100 yuan. Money can be put into coins many times. (2) there are 16 types of goods to choose from, and the price is 1-16 yuan respectively. The customer can enter the number of the goods to realize the choice of the goods. That is, a small keyboard (0-9 button) to complete, such as enter 15, enter 1, and then enter 5. (3) customers can choose the quantity needed after they have finished choosing the goods. You can choose up to three items at a time. It then shows the required amount and the total value of the coin. During the coin slot, the customer can cancel the operation by pressing the cancel key, and the coin will automatically withdraw.
Plat: VHDL | Size: 8184KB | Downloads: 0
xi 2017-10-09 14:50:27
Description: h.264 fpga http://soc.fudan.edu.cn/vip
Plat: Verilog | Size: 1411KB | Downloads: 3