何基 2017-10-21 20:18:18
Description: The use of VHDL language as a tool for the preparation of 8B10B codec
Plat: VHDL | Size: 68KB | Downloads: 0
LIWEI 2017-10-16 14:28:03
Description: alarm clock vhdl implemention
Plat: Quartus II | Size: 361KB | Downloads: 0
Farhan 2017-10-16 07:36:00
Description: testing testbench to device under test (dut)
Plat: VHDL | Size: 13KB | Downloads: 0
光临 2017-10-14 14:54:47
Description: VHDL has debugged OK in CPLD_EPM240, and LCD12864 shows English
Plat: C51 | Size: 44KB | Downloads: 0
Roger 2017-10-12 18:18:37
Description: e Formwork Experts for Wall and Slab formwork, Bridge and Tunnel forms, Climbing, Load-bearing and Safety Systems as well as architectural ...
Plat: Borland C++ | Size: 8KB | Downloads: 0
0531 2017-10-12 17:09:39
Description: carrier synchronization
Plat: VHDL | Size: 1099KB | Downloads: 0
姜勇宏 2017-10-10 14:47:16
Description: (1) coins and paper notes can be entered. The range of coin recognition is 5 cents and 1 yuan coins. The range of identification of notes is 1 yuan, 5 yuan, 10 yuan, 20 yuan, 50 yuan, 100 yuan. Money can be put into coins many times. (2) there are 16 types of goods to choose from, and the price is 1-16 yuan respectively. The customer can enter the number of the goods to realize the choice of the goods. That is, a small keyboard (0-9 button) to complete, such as enter 15, enter 1, and then enter 5. (3) customers can choose the quantity needed after they have finished choosing the goods. You can choose up to three items at a time. It then shows the required amount and the total value of the coin. During the coin slot, the customer can cancel the operation by pressing the cancel key, and the coin will automatically withdraw.
Plat: VHDL | Size: 8184KB | Downloads: 0
Isadora Stangarlin 2017-09-28 00:51:06
Description: Code developed in classroom
Plat: VHDL | Size: 1KB | Downloads: 0
Keita Ogawa 2017-09-27 21:25:47
Description: VHDL How to use CoreABC-IP with uart microsemi project
Plat: VHDL | Size: 2507KB | Downloads: 0
Keita Ogawa 2017-09-27 21:19:12
Description: VHDL How to use PLL-IP core microsemi project
Plat: VHDL | Size: 292KB | Downloads: 0
Keita Ogawa 2017-09-27 21:16:57
Description: VHDL generating of trig down signal microsemi project
Plat: VHDL | Size: 254KB | Downloads: 0
Keita Ogawa 2017-09-27 21:14:10
Description: VHDL generating of trig signal microsemi project
Plat: VHDL | Size: 254KB | Downloads: 0
Keita Ogawa 2017-09-27 21:11:03
Description: VHDL 3 phase of PWM microsemi project
Plat: VHDL | Size: 3664KB | Downloads: 0
fanfingsing 2017-09-25 15:49:04
Description: A one-dimensional transfer matrix method to calculate the phonon crystal structure, MIMO OFDM matlab simulation, For time-frequency analysis algorithm.
Plat: C-C++ | Size: 58KB | Downloads: 0
郭星辰 2017-09-22 16:06:29
Description: Two choose one, for FPGA programming beginner stage, a simple example, the use of decompression can be, Quartus II 9 (32-Bit) applications
Plat: VHDL | Size: 144KB | Downloads: 0
高军 2017-09-20 15:07:49
Description: Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry
Plat: VHDL | Size: 20KB | Downloads: 1
徐良 2017-09-13 11:07:44
Description: Test, signed and unsigned binary number addition, result comparison
Plat: Vivado | Size: 58KB | Downloads: 0
李诚 2017-09-13 09:22:01
Description: The SOPC system is built with Altera FPGA, and embedded C programming is used to realize the servo motor control.
Plat: C-C++ | Size: 30703KB | Downloads: 2
KevinZ 2017-09-12 15:12:32
Description: Simulating the functions of POC. In VHDL, with ISE.
Plat: VHDL | Size: 555KB | Downloads: 0
KevinZ 2017-09-12 15:10:36
Description: Simulating the tickets selling systems of metros. In VHDL, with ISE.
Plat: VHDL | Size: 25KB | Downloads: 1
KevinZ 2017-09-12 15:07:58
Description: Simulating the work theory of cpu. By VHDL in ISE.
Plat: VHDL | Size: 4208KB | Downloads: 1
KevinZ 2017-09-12 15:04:01
Description: Codes in doc. Simulating the tickets sales system of metros. With ISE, in VHDL.
Plat: VHDL | Size: 5175KB | Downloads: 0
薛佳琦 2017-09-12 14:00:03
Description: VHDL serial port conversion code
Plat: VHDL | Size: 469KB | Downloads: 0
祁家俊 2017-09-10 10:57:47
Description: Using VHDL language, through the VGA display Chinese characters on the screen
Plat: VHDL | Size: 1KB | Downloads: 0
Jane 2017-09-07 17:09:23
Description: a simply cpu design, vhdl quartus ii ,dsg gs h srh rsh rsh srjh srh
Plat: VHDL | Size: 1454KB | Downloads: 0
Art 2017-09-04 17:49:10
Description: BCH coder and decoder. Uses special DMA connection
Plat: VHDL | Size: 17KB | Downloads: 0
焦平劳 2017-09-03 10:43:18
Description: By matlab code, Has been successful debugging. M contains files can be directly run, Filtering summation way broadband beamforming.
Plat: PHP-PERL | Size: 5KB | Downloads: 0