wa哈哈哈 2018-05-24 21:14:23
Description: Very classic routine, suitable for beginners reference.
Plat: VHDL | Size: 169KB | Downloads: 0
2131131358 2018-05-24 15:50:39
Description: 38 decoders' schematic files, which can be compiled and simulated directly.
Plat: Verilog | Size: 1432KB | Downloads: 0
sayu 2018-05-21 13:52:06
Description: mouse overlay controller
Plat: Others | Size: 903KB | Downloads: 0
小玲娃 2018-05-21 09:57:39
Description: Black and white judgment experiment: Camera Black and white resolution and judgment, and use the test box LED light to display the experimental code.
Plat: VHDL | Size: 18KB | Downloads: 0
fastfastfast 2018-05-21 08:53:34
Description: vhdl vga color bar test program
Plat: VHDL | Size: 172KB | Downloads: 0
los_galacticos 2018-05-19 20:00:06
Description: Speech Recognation VHDL Code
Plat: VHDL | Size: 318KB | Downloads: 0
los_galacticos 2018-05-19 19:59:05
Description: Uart RS232 VHDL Code
Plat: VHDL | Size: 93KB | Downloads: 0
los_galacticos 2018-05-19 19:58:01
Description: Full-Adder VHDL Code
Plat: VHDL | Size: 394KB | Downloads: 0
AliReza2002 2018-05-19 16:15:09
Description: Code of VHDL for Full_Adder
Plat: VHDL | Size: 205KB | Downloads: 0
peterklaus321 2018-05-17 21:11:34
Description: this is my final upload
Plat: UNIX | Size: 89KB | Downloads: 0
mfk126 2018-05-16 15:12:20
Description: SPI data transmission, clock signal is 30.72MHz
Plat: Quartus II | Size: 161KB | Downloads: 0
JayS 2018-05-16 12:57:00
Description: Simple Majority Circuit and a sequential circuit
Plat: VHDL | Size: 74KB | Downloads: 0
JOHNSSSSSSS 2018-05-15 22:54:24
Description: led send card verilog
Plat: VHDL | Size: 40KB | Downloads: 0
liever18 2018-05-15 16:26:42
Description: The application of simple 8*8 dot matrix can realize the control of key to display.
Plat: VHDL | Size: 174KB | Downloads: 0
闭家锁的话 2018-05-15 13:52:11
Description: 1, must do: design and implement a 8 * 8 dot matrix scanning controller, stable display of a number or letter on the dot matrix, the color is red and green. 2, choose to do: display characters with 8 x 8 dot matrix, display one character each time, switch once a second, display the contents of "B", "U", "P", "T" and the first letter of the name. For example, Zhang San shows the contents of "B", "U", "P", "T", "Z" and "S".
Plat: VHDL | Size: 433KB | Downloads: 1
有风来过 2018-05-15 10:55:34
Description: The implementation of 32 bit adder in the VHDL language
Plat: VHDL | Size: 315KB | Downloads: 0
峨眉峰 2018-05-10 21:58:13
Description: 6 bit sine signal generator
Plat: VHDL | Size: 629KB | Downloads: 0
meisamb 2018-05-10 16:03:10
Description: This is a simple pattern generator in VGA format.
Plat: VHDL | Size: 18KB | Downloads: 0
meisamb 2018-05-10 16:00:57
Description: This project implements a simplified version of the Nintendo Entertainment System on an FPGA, that can execute Super Mario Bros.
Plat: VHDL | Size: 390KB | Downloads: 0
meisamb 2018-05-10 15:59:13
Description: This codes are examples for testing DVI output by FPGAs of xilinx.
Plat: VHDL | Size: 23KB | Downloads: 0
lala khan 2018-05-08 23:54:16
Description: a practical primer on verilog HDL synthesis
Plat: Others | Size: 4866KB | Downloads: 0
lala khan 2018-05-08 23:45:08
Description: The Verilog Golden Reference Guide is a compact quick reference guide to the Verilog hardware description language
Plat: VHDL | Size: 272KB | Downloads: 0
lxnww 2018-05-08 11:21:32
Description: FPGA program of matrix converters
Plat: VHDL | Size: 439KB | Downloads: 2
任红美 2018-05-07 20:07:00
Description: Implementation of ad0809 conversion state machine
Plat: VHDL | Size: 560KB | Downloads: 0
shilinpuerduo 2018-05-06 12:05:30
Description: USB_UART implementation on FPGA board, including transmitter, receivre, controller, initialization, and package
Plat: VHDL | Size: 1122KB | Downloads: 0
shilinpuerduo 2018-05-06 11:48:33
Description: vhdl implementation of receiver of USB ip based on UART
Plat: VHDL | Size: 1KB | Downloads: 0
shilinpuerduo 2018-05-06 11:47:11
Description: vhdl implementation of USB ip based on UART standard
Plat: VHDL | Size: 1KB | Downloads: 0
shilinpuerduo 2018-05-06 11:45:27
Description: USB ip implementation with VHDL based on UART standard
Plat: VHDL | Size: 1KB | Downloads: 0
ledhhh 2018-05-05 15:12:25
Description: The design of simple digital clock is realized by VHDL language programming based on the small foot experiment board and the peripheral panel. Three keys: mode key, digital key, and digital key reduction; four modes: normal mode, time mode, modulation mode, second mode; four LED lights: four modes indicating digital clock; six bits of digital tube from left to right per two unit respectively. Adjust the time mode, corresponding to the digital tube display adjustment value; decimal point DP display: left second, fourth, sixth digital tube DP light, in order to distinguish minutes and seconds.
Plat: VHDL | Size: 2KB | Downloads: 3
光速ZY 2018-04-29 22:19:47
Description: The simulation of CD4527(BCD proportional multiplier)
Plat: VHDL | Size: 2KB | Downloads: 1