enstab 2019-05-24 19:27:30
Description: Image compression using the wavelet algorithm
Plat: WINDOWS | Size: 236KB | Downloads: 0
Yitech 2019-05-24 13:53:37
Description: The book introduces the theory and practice of VHDL based on EDA technology with practicality and operability, conciseness and completeness.
Plat: VHDL | Size: 3962KB | Downloads: 0
imax16041998 2019-05-23 16:29:53
Description: this source design couter 16 bit by VHDL code
Plat: VHDL | Size: 208KB | Downloads: 0
imax16041998 2019-05-23 16:28:34
Description: this source design i2c by VHDL code
Plat: VHDL | Size: 45KB | Downloads: 0
瘾1581 2019-05-20 23:25:39
Description: Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale and language are required respectively): Functional requirements: Its input is two 8-bit unsigned binary integers X and Y, and a control signal S; the output signal is an 8-bit unsigned binary integer Z. The relationship between input and output is: when S = 1, Z = min (X, Y); when S = 0, Z = max (X, Y).
Plat: Vivado | Size: 10KB | Downloads: 0
alimalekibigdeli 2019-05-19 16:53:30
Description: This expression can be used to determine the modulus of the material in terms of the measured center deflection We, applied load Fo, and the geometric parameters of the laminated beam in a three-point bend test:
Plat: PHP | Size: 174KB | Downloads: 0
umbrella0923 2019-05-18 17:19:59
Description: Programs written in VHDL language and series-to-parallel conversion circuit implemented by SPI protocol
Plat: VHDL | Size: 4366KB | Downloads: 0
umbrella0923 2019-05-18 17:18:39
Description: Programs written in VHDL language and parallel-to-serial conversion circuit implemented by SPI protocol
Plat: VHDL | Size: 4320KB | Downloads: 0
umbrella0923 2019-05-18 17:16:46
Description: Using VHDL language to write programs to generate sinusoidal waves, including testbench files, has been simulated on Modelsim
Plat: VHDL | Size: 4335KB | Downloads: 0
umbrella0923 2019-05-18 17:14:21
Description: Using VHDL language to write programs to generate square waves, including testbench files, has been simulated on Modelsim
Plat: VHDL | Size: 4215KB | Downloads: 0
umbrella0923 2019-05-18 17:12:56
Description: Using VHDL language to write programs to generate triangular waves, including testbench files, has been simulated on Modelsim
Plat: VHDL | Size: 4235KB | Downloads: 0
umbrella0923 2019-05-18 17:10:36
Description: Using VHDL language to write programs to generate sawtooth waves, including testbench files, has been simulated on modelsim.
Plat: VHDL | Size: 4205KB | Downloads: 0
star112 2019-05-17 21:33:53
Description: Bitcoin mining circuit in VHDL
Plat: WINDOWS | Size: 124KB | Downloads: 0
star112 2019-05-17 21:16:30
Description: AES algorithm implementation in VHDL.
Plat: WINDOWS | Size: 495KB | Downloads: 1
swoon 2019-05-15 05:23:44
Description: Scan HDD into computer
Plat: WINDOWS | Size: 3030KB | Downloads: 0
Duy Cuong 2019-05-14 01:45:12
Description: bui duy cuongfff dep trai
Plat: Python | Size: 31KB | Downloads: 0
johnmatlab 2019-05-12 18:08:53
Description: Learn simulink through this interactive lecture. Three phase input is rww1
Plat: matlab | Size: 39KB | Downloads: 0
爱喝可乐的猫 2019-05-11 20:12:13
Description: Use frequency divider and digital tube driver to make digital tube display 1-8 further 1-8 right shift cycle
Plat: VHDL | Size: 1657KB | Downloads: 1
weiwei0417 2019-05-11 15:47:12
Description: VHDL and verilo configuration files in VIM Windows Environment
Plat: VHDL | Size: 12KB | Downloads: 0
chulan 2019-05-11 15:40:50
Description: The three-person voter based on VHDL implemented in QUARTUS has been successfully simulated.
Plat: VHDL | Size: 126KB | Downloads: 0
shahr 2019-05-11 15:01:39
Description: lan vhdl test lan vhdl test
Plat: VHDL | Size: 1011KB | Downloads: 0
SEEYO 2019-05-11 02:53:24
Description: MULTIPLIER VHDL CODE
Plat: VHDL | Size: 53KB | Downloads: 0
SEEYO 2019-05-11 02:51:35
Description: BINARY ADDER CODING IN VHDL
Plat: VHDL | Size: 1470KB | Downloads: 0
SEEYO 2019-05-11 02:50:25
Description: ALU CODE PROGRAMME FOR ALL ALU PART
Plat: VHDL | Size: 3189KB | Downloads: 0
SEEYO 2019-05-11 02:47:03
Description: COMPRESSION OF ALL DIGITAL ADDER WITH IMPLEMENT IN VHDL PROGRAMMING
Plat: VHDL | Size: 291KB | Downloads: 0
buganlex 2019-05-10 04:42:00
Description: usbfhfdhjdhfdhvbfbfrvgggg
Plat: VHDL | Size: 9KB | Downloads: 0
Overflag 2019-05-09 22:55:53
Description: Platform: ALTERA Cyclone IV EP4CE10F17C8. Clock 50MHz (Zircon Technology A4 Development Board) Function: A full scale within an octave. The half tone control is to press two full tone keys beside the half tone at the same time.
Plat: VHDL | Size: 3817KB | Downloads: 0
USTCer1322 2019-05-09 00:07:12
Description: First use Matlab to generate a non-negative sine wave and then sample 1024 points and 8 bits of data, and save it to mystorage.mif. Then use the MegaWizard in Quartus ll to generate a 1024*8bits memory (ram/rom) and initialize the memory with the above sine wave data. Then write the VHDL program to output the data to the DA port, compile and simulate. Finally, add a signaltapl file for the project, set the parameters, compile, download to the target board without error, and watch the data and waveform output to the DA port in signaltap ll.
Plat: VHDL | Size: 17981KB | Downloads: 0
USTCer1322 2019-05-09 00:04:55
Description: The keyboard array is driven by cyclically outputting "1110, 1101, 1011, 0111" to the four column control signals of the 4x4 keyboard array, and each of the output column sequences is followed by reading the corresponding four row signals. It is judged which of the 16 keys is pressed by the read data or status, and the state is encoded and output.
Plat: VHDL | Size: 14565KB | Downloads: 1
USTCer1322 2019-05-09 00:02:31
Description: The divider design divides the high frequency clock signal to a low frequency signal.
Plat: VHDL | Size: 14356KB | Downloads: 2