EasyFPGA030.part1

Directory: VHDL-FPGA-Verilog
Plat: Visual C++
Size: 8621KB
Downloads: 92
Upload time: 2009-09-24 16:13:53
Uploader: 波波1973
Description:   EasyFPGA030 development board CD-ROM 1

File list:
74hc138
.......\74hc138.pdf
.......\74hc138.prj
.......\74hc138.prj.convert.8.5.bak
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\decoder_38.adb
.......\........\.....\decoder_38.dtf
.......\........\.....\..............\verify.log
.......\........\.....\decoder_38.ide_des
.......\........\.....\decoder_38.pdb
.......\........\.....\decoder_38.pdb.depends
.......\........\.....\decoder_38.tcl
.......\........\.....\decoder_38_1_fp
.......\........\.....\...............\decoder_38.log
.......\........\.....\...............\decoder_38.pro
.......\........\.....\decoder_38_ba.sdf
.......\........\.....\decoder_38_ba.v
.......\........\.....\decoder_38_fp
.......\........\.....\.............\decoder_38.pro
.......\........\.....\designer.log
.......\........\.....\simulation
.......\hdl
.......\...\74hc138.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\decoder_38
.......\..........\........\..........\verilog.psm
.......\..........\........\..........\_primary.dat
.......\..........\........\..........\_primary.dbs
.......\..........\........\..........\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\.....\vlogzyq214
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\backup
.......\.........\......\decoder_38.srr
.......\.........\coreip
.......\.........\decoder_38.areasrr
.......\.........\decoder_38.edn
.......\.........\decoder_38.fse
.......\.........\decoder_38.htm
.......\.........\decoder_38.map
.......\.........\decoder_38.pdc
.......\.........\decoder_38.sap
.......\.........\decoder_38.sdf
.......\.........\decoder_38.so
.......\.........\decoder_38.srd
.......\.........\decoder_38.srm
.......\.........\decoder_38.srr
.......\.........\decoder_38.srs
.......\.........\decoder_38.szr
.......\.........\decoder_38.tlg
.......\.........\decoder_38_sdc.sdc
.......\.........\decoder_38_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\decoder_38.plg
.......\.........\......\decoder_38_flink.htm
.......\.........\......\decoder_38_srr.htm
.......\.........\......\decoder_38_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74HC151
.......\74hc151
.......\.......\74hc151.prj
.......\.......\component
.......\.......\constraint
.......\.......\coreconsole
.......\.......\designer
.......\.......\........\impl1
.......\.......\........\.....\designer.log
.......\.......\........\.....\MUX8_1.ide_des
.......\.......\........\.....\MUX8_1.tcl
.......\.......\........\.....\MUX8_1_1.adb

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