altera_sdram

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 2328KB
Downloads: 57
Upload time: 2009-05-24 13:13:53
Uploader: Esarh
Description:   SDRAM controller VHDL code FGPA and implementation of integrated

File list:
SDRAM
.....\DOC
.....\...\micron_sdram.pdf
.....\...\README.TXT
.....\...\sdr_sdram.pdf
.....\MODEL
.....\.....\mt48lc8m16a2.v
.....\ROUTE
.....\.....\PLL1.V
.....\.....\sdr_sdram.csf
.....\.....\sdr_sdram.esf
.....\.....\sdr_sdram.vqm
.....\simulation
.....\..........\MODELSIM.INI
.....\..........\README.TXT
.....\..........\SDRAM.MPF
.....\..........\sdr_sdram_tb.v
.....\..........\VSIM.WLF
.....\..........\WORK
.....\..........\....\altclklock
.....\..........\....\..........\VERILOG.ASM
.....\..........\....\..........\_PRIMARY.DAT
.....\..........\....\..........\_PRIMARY.VHD
.....\..........\....\COMMAND
.....\..........\....\.......\VERILOG.PSM
.....\..........\....\.......\_PRIMARY.DAT
.....\..........\....\.......\_PRIMARY.VHD
.....\..........\....\control_interface
.....\..........\....\.................\VERILOG.PSM
.....\..........\....\.................\_PRIMARY.DAT
.....\..........\....\.................\_PRIMARY.VHD
.....\..........\....\mt48lc8m16a2
.....\..........\....\............\VERILOG.ASM
.....\..........\....\............\_PRIMARY.DAT
.....\..........\....\............\_PRIMARY.VHD
.....\..........\....\PLL1
.....\..........\....\....\VERILOG.ASM
.....\..........\....\....\_PRIMARY.DAT
.....\..........\....\....\_PRIMARY.VHD
.....\..........\....\sdr_data_path
.....\..........\....\.............\VERILOG.PSM
.....\..........\....\.............\_PRIMARY.DAT
.....\..........\....\.............\_PRIMARY.VHD
.....\..........\....\sdr_sdram
.....\..........\....\.........\VERILOG.PSM
.....\..........\....\.........\_PRIMARY.DAT
.....\..........\....\.........\_PRIMARY.VHD
.....\..........\....\sdr_sdram_tb
.....\..........\....\............\VERILOG.PSM
.....\..........\....\............\_PRIMARY.DAT
.....\..........\....\............\_PRIMARY.VHD
.....\..........\....\_INFO
.....\SOURCE
.....\......\altclklock.v
.....\......\Command.v
.....\......\compile_all.v
.....\......\control_interface.v
.....\......\Params.v
.....\......\PLL1.V
.....\......\REV_1
.....\......\.....\sdr_sdram.acf
.....\......\.....\sdr_sdram.edf
.....\......\.....\sdr_sdram.fit
.....\......\.....\sdr_sdram.fse
.....\......\.....\sdr_sdram.hex
.....\......\.....\sdr_sdram.hif
.....\......\.....\sdr_sdram.mmf
.....\......\.....\sdr_sdram.ndb
.....\......\.....\sdr_sdram.pin
.....\......\.....\sdr_sdram.pof
.....\......\.....\sdr_sdram.rpt
.....\......\.....\sdr_sdram.sat
.....\......\.....\sdr_sdram.snf
.....\......\.....\sdr_sdram.sof
.....\......\.....\sdr_sdram.srm
.....\......\.....\sdr_sdram.srr
.....\......\.....\sdr_sdram.srs
.....\......\.....\sdr_sdram.sxr
.....\......\.....\sdr_sdram.tlg
.....\......\.....\sdr_sdram.ttf
.....\......\sdr_data_path.v
.....\......\sdr_sdram.v
.....\......\TEST.PRD
.....\......\TEST.PRJ
.....\synthesis
.....\.........\synplicity
.....\.........\..........\altclklock.v
.....\.........\..........\Command.v
.....\.........\..........\compile_all.v
.....\.........\..........\control_interface.v
.....\.........\..........\PLL1.V
.....\.........\..........\sdr_sdram.prj
.....\.........\..........\VER1
.....\.........\..........\....\sdr_sdram.srr

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