fir

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 888KB
Downloads: 1523
Upload time: 2008-05-13 15:51:59
Uploader: rockyking
Description:   VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.

File list:
fir
...\fir
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...\...\db
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...\...\..\fir.cbx.xml
...\...\..\fir.cmp.cdb
...\...\..\fir.cmp.hdb
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...\...\..\fir.cmp.rdb
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...\...\..\fir.cmp0.ddb
...\...\..\fir.dbp
...\...\..\fir.db_info
...\...\..\fir.eco.cdb
...\...\..\fir.eds_overflow
...\...\..\fir.fit.qmsg
...\...\..\fir.hier_info
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...\...\..\fir.psp
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...\...\..\fir.rtlv_sg.cdb
...\...\..\fir.rtlv_sg_swap.cdb
...\...\..\fir.sgdiff.cdb
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...\...\..\fir.signalprobe.cdb
...\...\..\fir.sim.hdb
...\...\..\fir.sim.qmsg
...\...\..\fir.sim.rdb
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...\...\..\fir.sld_design_entry.sci
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...\FIR设计107101286.doc

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