Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 1666KB
Downloads: 1398
Upload time: 2008-04-09 22:06:01
Uploader: 高超
Description:   Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.

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