VHDL-XILINX-EXAMPLE26

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 3601KB
Downloads: 1208
Upload time: 2008-03-29 00:23:20
Uploader: hawd
Description:   

File list:
XC95
....\EX1
....\...\dpm_net
....\...\.......\EX1.edf
....\...\ex1
....\...\...\chips
....\...\...\.....\ver1
....\...\...\.....\....\ver1.cst
....\...\...\.....\....\ver1.rpt
....\...\...\.....\....\ver1.ws
....\...\...\.....\ver1-Optimized
....\...\...\.....\..............\ver1-Optimized.cst
....\...\...\.....\..............\ver1-Optimized.rpt
....\...\...\.....\..............\ver1-Optimized.ws
....\...\...\.....\ver2
....\...\...\.....\....\ver2.cst
....\...\...\.....\....\ver2.rpt
....\...\...\.....\....\ver2.ws
....\...\...\.....\ver2-Optimized
....\...\...\.....\..............\ver2-Optimized.cst
....\...\...\.....\..............\ver2-Optimized.rpt
....\...\...\.....\..............\ver2-Optimized.ws
....\...\...\.....\ver3
....\...\...\.....\....\ver3.cst
....\...\...\.....\....\ver3.rpt
....\...\...\.....\....\ver3.ws
....\...\...\.....\ver3-Optimized
....\...\...\.....\..............\ver3-Optimized.cst
....\...\...\.....\..............\ver3-Optimized.rpt
....\...\...\.....\..............\ver3-Optimized.ws
....\...\...\ex1.exp
....\...\...\files
....\...\...\.....\L0.rpt
....\...\...\.....\L2.rpt
....\...\...\workdirs
....\...\...\........\WORK
....\...\...\........\....\Anal.info
....\...\...\........\....\Anal.out
....\...\...\........\....\EX1.hnl
....\...\...\........\....\EX1.mra
....\...\...\........\....\EX1.out
....\...\...\........\....\EX1.sim
....\...\...\........\....\EX1.sts
....\...\...\........\....\EX1.syn
....\...\...\........\....\EX1__BEHV.sim
....\...\...\........\....\EX1__BEHV.syn
....\...\ex1.alb
....\...\ex1.EDF
....\...\ex1.er
....\...\ex1.jed
....\...\ex1.log
....\...\ex1.opt
....\...\ex1.prj
....\...\ex1.tve
....\...\ex1.ucf
....\...\ex1.vhd
....\...\ex11.SCH
....\...\express.ini
....\...\lib
....\...\...\EX1.BLK
....\...\...\EX1.DIR
....\...\...\EX1.FIG
....\...\...\EX1.FLG
....\...\...\EX1.GNR
....\...\...\EX1.HDR
....\...\...\EX1.ID
....\...\...\EX1.INI
....\...\...\EX1.MAP
....\...\...\EX1.MOD
....\...\...\EX1.PIN
....\...\...\EX1.SYM
....\...\...\EX1.SYN
....\...\...\EX1.VIS
....\...\LOGIBLOX.INI
....\...\logiblox.log
....\...\netlist.log
....\...\S95.log
....\...\time_sim.edn
....\...\xproj
....\...\.....\ex1.xpj
....\...\.....\project.not
....\...\.....\ver1
....\...\.....\....\ex1.ngo
....\...\.....\....\netlist.lst
....\...\.....\....\rev1
....\...\.....\....\....\command.his
....\...\.....\....\....\ex1.bld
....\...\.....\....\....\ex1.ctl
....\...\.....\....\....\ex1.data
....\...\.....\....\....\ex1.gyd
....\...\.....\....\....\ex1.jed
....\...\.....\....\....\ex1.log
....\...\.....\....\....\ex1.mfd
....\...\.....\....\....\ex1.mod
....\...\.....\....\....\ex1.nga
....\...\.....\....\....\ex1.ngd
....\...\.....\....\....\ex1.pnx
....\...\.....\....\....\ex1.rpt
....\...\.....\....\....\ex1.tim
....\...\.....\....\....\ex1.ucf

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