01_counter_design

Directory: Other systems
Plat: Verilog
Size: 44KB
Downloads: 0
Upload time: 2020-04-01 20:17:33
Uploader: NEVILLE LI
Description:   counter xilinx FPGA VHDL

File list:
01_counter_design, 0 , 2017-06-21
01_counter_design\core, 0 , 2020-04-01
01_counter_design\dev, 0 , 2018-06-18
01_counter_design\dev\counter_design.qpf, 1349 , 2017-06-21
01_counter_design\dev\counter_design.qsf, 2179 , 2018-06-18
01_counter_design\dev\counter_design.qws, 1041 , 2018-06-18
01_counter_design\dev\counter_design_assignment_defaults.qdf, 49803 , 2018-06-18
01_counter_design\dev\db, 0 , 2018-06-18
01_counter_design\dev\db\counter_design.cbx.xml, 96 , 2018-06-18
01_counter_design\dev\db\counter_design.cmp.rdb, 3448 , 2018-06-18
01_counter_design\dev\db\counter_design.db_info, 140 , 2018-06-18
01_counter_design\dev\db\counter_design.hif, 178 , 2018-06-18
01_counter_design\dev\db\counter_design.logic_util_heuristic.dat, 0 , 2018-06-18
01_counter_design\dev\db\counter_design.map.hdb, 8662 , 2018-06-18
01_counter_design\dev\db\counter_design.map.qmsg, 3294 , 2018-06-18
01_counter_design\dev\db\counter_design.map.rdb, 1041 , 2018-06-18
01_counter_design\dev\db\counter_design.pre_map.hdb, 8583 , 2018-06-18
01_counter_design\dev\db\counter_design.pti_db_list.ddb, 238 , 2018-06-18
01_counter_design\dev\db\counter_design.sld_design_entry.sci, 270 , 2018-06-18
01_counter_design\dev\db\counter_design.smart_action.txt, 8 , 2018-06-18
01_counter_design\dev\db\counter_design.tis_db_list.ddb, 238 , 2018-06-18
01_counter_design\dev\db\prev_cmp_counter_design.qmsg, 3531 , 2017-06-21
01_counter_design\dev\output_files, 0 , 2018-06-18
01_counter_design\dev\output_files\counter_design.flow.rpt, 5041 , 2018-06-18
01_counter_design\dev\output_files\counter_design.map.rpt, 12195 , 2018-06-18
01_counter_design\dev\output_files\counter_design.map.summary, 226 , 2018-06-18
01_counter_design\doc, 0 , 2020-04-01
01_counter_design\sim, 0 , 2020-04-01
01_counter_design\src, 0 , 2017-06-21
01_counter_design\src\counter_design.v, 292 , 2017-06-21
01_counter_design\src\counter_design.v.bak, 296 , 2017-06-21

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