0_19_Sdram_Control

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 3616KB
Downloads: 2
Upload time: 2020-03-26 08:56:55
Uploader: ZDCHXGG
Description:   Using Verilog language to realize the initial configuration of SDRAM and the operation of reading, writing and refreshing, with Modelsim simulation module

File list:
doc, 0 , 2020-03-20
doc\History, 0 , 2020-03-20
doc\History\SDRAM时序.~(1).SchDoc.Zip, 1464 , 2020-01-26
doc\History\SDRAM时序.~(10).SchDoc.Zip, 2253 , 2020-01-26
doc\History\SDRAM时序.~(11).SchDoc.Zip, 2343 , 2020-01-26
doc\History\SDRAM时序.~(12).SchDoc.Zip, 2333 , 2020-01-26
doc\History\SDRAM时序.~(13).SchDoc.Zip, 2531 , 2020-01-26
doc\History\SDRAM时序.~(14).SchDoc.Zip, 2534 , 2020-01-26
doc\History\SDRAM时序.~(15).SchDoc.Zip, 2536 , 2020-01-26
doc\History\SDRAM时序.~(2).SchDoc.Zip, 1480 , 2020-01-26
doc\History\SDRAM时序.~(3).SchDoc.Zip, 1642 , 2020-01-26
doc\History\SDRAM时序.~(4).SchDoc.Zip, 1753 , 2020-01-26
doc\History\SDRAM时序.~(5).SchDoc.Zip, 1761 , 2020-01-26
doc\History\SDRAM时序.~(6).SchDoc.Zip, 1835 , 2020-01-26
doc\History\SDRAM时序.~(7).SchDoc.Zip, 1964 , 2020-01-26
doc\History\SDRAM时序.~(8).SchDoc.Zip, 2008 , 2020-01-26
doc\History\SDRAM时序.~(9).SchDoc.Zip, 2218 , 2020-01-26
doc\SDRAM时序.SchDoc, 12800 , 2020-01-26
doc\~$SDRAM模式和时序.xlsx, 165 , 2020-01-26
doc\状态机.vsdx, 33543 , 2020-01-27
img, 0 , 2020-03-20
img\sdram_control_top1.PNG, 36654 , 2017-04-01
img\sdram_control_top2.PNG, 7302 , 2017-04-01
img\sdram_control_top3.PNG, 7375 , 2017-04-01
ip, 0 , 2020-03-23
ip\fifo_rd.qip, 348 , 2020-03-23
ip\fifo_rd.v, 7650 , 2020-03-23
ip\fifo_rd_bb.v, 6383 , 2020-03-23
ip\fifo_wr.qip, 348 , 2020-03-23
ip\fifo_wr.v, 7650 , 2020-03-23
ip\fifo_wr_bb.v, 6383 , 2020-03-23
ip\greybox_tmp, 0 , 2020-03-20
ip\greybox_tmp\cbx_args.txt, 367 , 2017-04-01
prj, 0 , 2020-03-26
prj\db, 0 , 2020-03-26
prj\db\.ipregen.qmsg, 2718 , 2020-03-23
prj\db\a_gray2bin_ugb.tdf, 1646 , 2020-02-12
prj\db\a_graycounter_pjc.tdf, 3764 , 2020-02-12
prj\db\a_graycounter_t57.tdf, 3667 , 2020-02-12
prj\db\alt_synch_pipe_ikd.tdf, 2197 , 2020-02-12
prj\db\alt_synch_pipe_jkd.tdf, 2197 , 2020-02-12
prj\db\altsyncram_jc11.tdf, 20998 , 2020-02-12
prj\db\cmpr_f66.tdf, 2296 , 2020-02-12
prj\db\dcfifo_ghl1.tdf, 7652 , 2020-02-12
prj\db\dffpipe_3dc.tdf, 1802 , 2020-02-12
prj\db\dffpipe_gd9.tdf, 1578 , 2020-02-12
prj\db\dffpipe_hd9.tdf, 1741 , 2020-02-12
prj\db\dffpipe_id9.tdf, 1741 , 2020-02-12
prj\db\logic_util_heursitic.dat, 0 , 2020-03-02
prj\db\prev_cmp_Sdram_Control.qmsg, 4093 , 2020-03-23
prj\db\Sdram_Control.db_info, 140 , 2020-03-26
prj\db\Sdram_Control.ipinfo, 163 , 2020-03-26
prj\db\Sdram_Control.sld_design_entry.sci, 202 , 2020-03-26
prj\db\Sdram_Control_partition_pins.json, 6486 , 2020-03-23
prj\fifo_rd.qip, 0 , 2017-04-01
prj\fifo_wr.qip, 0 , 2017-04-01
prj\greybox_tmp, 0 , 2020-03-20
prj\greybox_tmp\cbx_args.txt, 389 , 2020-03-23
prj\incremental_db, 0 , 2020-03-20
prj\incremental_db\compiled_partitions, 0 , 2020-03-26
prj\incremental_db\compiled_partitions\Sdram_Control.db_info, 140 , 2020-03-26
prj\incremental_db\README, 653 , 2017-12-08
prj\output_files, 0 , 2020-03-23
prj\output_files\Sdram_Control.asm.rpt, 7517 , 2020-02-12
prj\output_files\Sdram_Control.done, 26 , 2020-03-23
prj\output_files\Sdram_Control.eda.rpt, 7946 , 2020-02-12
prj\output_files\Sdram_Control.fit.rpt, 531065 , 2020-02-12
prj\output_files\Sdram_Control.fit.smsg, 703 , 2020-02-12
prj\output_files\Sdram_Control.fit.summary, 634 , 2020-02-12
prj\output_files\Sdram_Control.flow.rpt, 12180 , 2020-03-23
prj\output_files\Sdram_Control.jdi, 232 , 2020-02-12
prj\output_files\Sdram_Control.map.rpt, 46360 , 2020-03-23
prj\output_files\Sdram_Control.map.smsg, 1855 , 2020-03-23
prj\output_files\Sdram_Control.map.summary, 485 , 2020-03-23
prj\output_files\Sdram_Control.pin, 32602 , 2020-02-12
prj\output_files\Sdram_Control.sof, 358660 , 2020-02-12
prj\output_files\Sdram_Control.sta.rpt, 847372 , 2020-02-12
prj\output_files\Sdram_Control.sta.summary, 1392 , 2020-02-12
prj\Sdram_Control.ipregen.rpt, 3851 , 2020-03-23
prj\Sdram_Control.out.sdc, 3599 , 2020-01-29
prj\Sdram_Control.qpf, 1295 , 2017-04-01
prj\Sdram_Control.qsf, 7060 , 2020-03-26
prj\Sdram_Control.qws, 10410 , 2020-03-26
prj\Sdram_Control_assignment_defaults.qdf, 57534 , 2020-01-26
prj\Sdram_Control_nativelink_simulation.rpt, 1054 , 2020-03-23
prj\simulation, 0 , 2020-03-20
prj\simulation\modelsim, 0 , 2020-03-23
prj\simulation\modelsim\modelsim.ini, 93532 , 2020-03-23
prj\simulation\modelsim\msim_transcript, 71758 , 2020-03-23
prj\simulation\modelsim\rtl_work, 0 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt, 0 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib.qdb, 49152 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib1_0.qdb, 32768 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib1_0.qpg, 16384 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib1_0.qtl, 51553 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib2_0.qdb, 32768 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib2_0.qpg, 40960 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib2_0.qtl, 20792 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib3_0.qdb, 32768 , 2020-03-23
prj\simulation\modelsim\rtl_work\@_opt\_lib3_0.qpg, 16384 , 2020-03-23

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