0_18_SCCB

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 33KB
Downloads: 3
Upload time: 2020-03-26 08:48:39
Uploader: ZDCHXGG
Description:   Using Verilog language to realize SCCB protocol of interface configuration of camera ov7670

File list:
doc, 0 , 2019-12-25
img, 0 , 2019-12-25
ip, 0 , 2020-02-05
pcb, 0 , 2019-12-25
prj, 0 , 2020-03-26
prj\db, 0 , 2020-03-26
prj\db\logic_util_heursitic.dat, 0 , 2020-02-05
prj\db\prev_cmp_SCCB.qmsg, 4708 , 2020-02-05
prj\db\SCCB.db_info, 140 , 2020-03-26
prj\db\SCCB.ipinfo, 163 , 2020-03-26
prj\db\SCCB.sld_design_entry.sci, 202 , 2020-03-26
prj\incremental_db, 0 , 2020-03-20
prj\incremental_db\compiled_partitions, 0 , 2020-03-26
prj\incremental_db\compiled_partitions\SCCB.db_info, 140 , 2020-03-26
prj\incremental_db\README, 653 , 2020-02-05
prj\output_files, 0 , 2020-03-20
prj\output_files\SCCB.done, 26 , 2020-02-05
prj\output_files\SCCB.flow.rpt, 7669 , 2020-02-05
prj\output_files\SCCB.map.rpt, 28385 , 2020-02-05
prj\output_files\SCCB.map.smsg, 288 , 2020-02-05
prj\output_files\SCCB.map.summary, 469 , 2020-02-05
prj\SCCB.qpf, 1292 , 2020-02-05
prj\SCCB.qsf, 3276 , 2020-03-26
prj\SCCB.qws, 762 , 2020-03-26
prj\SCCB_assignment_defaults.qdf, 56026 , 2020-03-20
rtl, 0 , 2020-03-20
rtl\SCCB.v, 18896 , 2020-03-26
rtl\SCCB.v.bak, 18728 , 2020-02-05
testbench, 0 , 2019-12-25

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