培训代码

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 2KB
Downloads: 0
Upload time: 2020-01-14 00:02:24
Uploader: 来战何人
Description:   Sequence detection with finite state machine

File list:
adder.v, 341 , 2014-11-11
AD转换.v, 10099 , 2014-11-11
freq_div.v, 549 , 2014-11-11
Read.txt, 86 , 2014-11-11
有限状态机.v, 1114 , 2014-11-11

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