project_1

Directory: Other systems
Plat: VHDL
Size: 1088KB
Downloads: 0
Upload time: 2020-01-11 09:54:11
Uploader: jbro
Description:   Sample project on xillinx fpga

File list:
project_1\project_1.cache, 0 , 2018-12-29
project_1\project_1.cache\ip, 0 , 2018-12-29
project_1\project_1.cache\ip\2018.3, 0 , 2018-12-29
project_1\project_1.cache\wt, 0 , 2018-12-29
project_1\project_1.cache\wt\gui_handlers.wdf, 3528 , 2018-12-29
project_1\project_1.cache\wt\java_command_handlers.wdf, 1123 , 2018-12-29
project_1\project_1.cache\wt\project.wpc, 121 , 2018-12-29
project_1\project_1.cache\wt\synthesis.wdf, 5392 , 2018-12-29
project_1\project_1.cache\wt\synthesis_details.wdf, 100 , 2018-12-29
project_1\project_1.cache\wt\webtalk_pa.xml, 4091 , 2018-12-29
project_1\project_1.hw, 0 , 2018-12-29
project_1\project_1.hw\hw_1, 0 , 2018-12-29
project_1\project_1.hw\hw_1\hw.xml, 787 , 2018-12-29
project_1\project_1.hw\hw_1\wave, 0 , 2018-12-29
project_1\project_1.hw\project_1.lpr, 343 , 2018-12-29
project_1\project_1.ip_user_files, 0 , 2018-12-29
project_1\project_1.runs, 0 , 2018-12-29
project_1\project_1.runs\.jobs, 0 , 2018-12-29
project_1\project_1.runs\.jobs\vrs_config_1.xml, 510 , 2018-12-29
project_1\project_1.runs\.jobs\vrs_config_2.xml, 510 , 2018-12-29
project_1\project_1.runs\.jobs\vrs_config_3.xml, 331 , 2018-12-29
project_1\project_1.runs\.jobs\vrs_config_4.xml, 510 , 2018-12-29
project_1\project_1.runs\.jobs\vrs_config_5.xml, 510 , 2018-12-29
project_1\project_1.runs\.jobs\vrs_config_6.xml, 331 , 2018-12-29
project_1\project_1.runs\impl_1, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.init_design.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_1\.init_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.opt_design.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_1\.opt_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.place_design.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_1\.place_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.route_design.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_1\.route_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.vivado.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_1\.vivado.error.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.Vivado_Implementation.queue.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.write_bitstream.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_1\.write_bitstream.error.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_1\.Xil, 0 , 2018-12-29
project_1\project_1.runs\impl_1\gen_run.xml, 6471 , 2018-12-29
project_1\project_1.runs\impl_1\htr.txt, 403 , 2018-12-29
project_1\project_1.runs\impl_1\init_design.pb, 5171 , 2018-12-29
project_1\project_1.runs\impl_1\ISEWrap.js, 7308 , 2018-12-29
project_1\project_1.runs\impl_1\ISEWrap.sh, 1623 , 2018-12-29
project_1\project_1.runs\impl_1\opt_design.pb, 11689 , 2018-12-29
project_1\project_1.runs\impl_1\place_design.pb, 13444 , 2018-12-29
project_1\project_1.runs\impl_1\project.wdf, 3626 , 2018-12-29
project_1\project_1.runs\impl_1\route_design.pb, 13069 , 2018-12-29
project_1\project_1.runs\impl_1\rundef.js, 1396 , 2018-12-29
project_1\project_1.runs\impl_1\runme.bat, 229 , 2018-12-29
project_1\project_1.runs\impl_1\runme.log, 29974 , 2018-12-29
project_1\project_1.runs\impl_1\runme.sh, 1255 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG.tcl, 6126 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG.vdi, 29787 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_bus_skew_routed.pb, 30 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_bus_skew_routed.rpt, 891 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_bus_skew_routed.rpx, 1048 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_clock_utilization_routed.rpt, 10161 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_control_sets_placed.rpt, 2976 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_drc_opted.pb, 37 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_drc_opted.rpt, 4550 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_drc_opted.rpx, 5779 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_drc_routed.pb, 37 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_drc_routed.rpt, 4988 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_drc_routed.rpx, 6426 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_io_placed.rpt, 99648 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_methodology_drc_routed.pb, 52 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_methodology_drc_routed.rpt, 8788 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_methodology_drc_routed.rpx, 13384 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_opt.dcp, 134150 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_placed.dcp, 151548 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_power_routed.rpt, 7651 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_power_routed.rpx, 28957 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_power_summary_routed.pb, 722 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_route_status.pb, 43 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_route_status.rpt, 588 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_routed.dcp, 160246 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_timing_summary_routed.pb, 52 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_timing_summary_routed.rpt, 8690 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_timing_summary_routed.rpx, 14041 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_utilization_placed.pb, 276 , 2018-12-29
project_1\project_1.runs\impl_1\SEVEN_SEG_utilization_placed.rpt, 8764 , 2018-12-29
project_1\project_1.runs\impl_1\vivado.jou, 705 , 2018-12-29
project_1\project_1.runs\impl_1\vivado.pb, 16 , 2018-12-29
project_1\project_1.runs\impl_1\write_bitstream.pb, 5511 , 2018-12-29
project_1\project_1.runs\impl_2, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.init_design.begin.rst, 182 , 2018-12-29
project_1\project_1.runs\impl_2\.init_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.opt_design.begin.rst, 182 , 2018-12-29
project_1\project_1.runs\impl_2\.opt_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.place_design.begin.rst, 182 , 2018-12-29
project_1\project_1.runs\impl_2\.place_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.route_design.begin.rst, 182 , 2018-12-29
project_1\project_1.runs\impl_2\.route_design.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.vivado.begin.rst, 180 , 2018-12-29
project_1\project_1.runs\impl_2\.vivado.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.Vivado_Implementation.queue.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.write_bitstream.begin.rst, 181 , 2018-12-29
project_1\project_1.runs\impl_2\.write_bitstream.end.rst, 0 , 2018-12-29
project_1\project_1.runs\impl_2\.Xil, 0 , 2018-12-29

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