FIR

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 51KB
Downloads: 0
Upload time: 2019-05-19 22:37:59
Uploader: 西电小勇
Description:   A 1MHz FIR low pass filter is designed. (1) The clock signal frequency is 16MHz; (2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz;

File list:
FIR\FIR.cr.mti, 513 , 2019-04-11
FIR\FIR.mpf, 98251 , 2019-04-11
FIR\FIR.v, 3329 , 2019-04-11
FIR\FIR.v.bak, 3329 , 2019-04-11
FIR\FIR_tb.v, 344 , 2019-04-11
FIR\FIR_tb.v.bak, 344 , 2019-04-11
FIR\vsim.wlf, 57344 , 2019-04-11
FIR\work\_info, 1232 , 2019-04-11
FIR\work\_lib.qdb, 49152 , 2019-04-11
FIR\work\_lib1_1.qdb, 32768 , 2019-04-11
FIR\work\_lib1_1.qpg, 81920 , 2019-04-11
FIR\work\_lib1_1.qtl, 129450 , 2019-04-11
FIR\work\_vmake, 29 , 2019-04-11
FIR\work, 0 , 2019-04-11
FIR, 0 , 2019-04-11

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