OpenMIPS_VerilogHDL_Study_v1.0

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 433KB
Downloads: 1
Upload time: 2019-05-06 19:19:38
Uploader: lllllllllz
Description:   OpenMIPS_Verilog HDL_Study_v1.0, the implementation of Verilog code for a mips-based cpu.

File list:
OpenMIPS_VerilogHDL_Study_v1.0\min_sopc\data_ram.v, 3324 , 2014-02-23
OpenMIPS_VerilogHDL_Study_v1.0\min_sopc\inst_rom.v, 2339 , 2014-02-07
OpenMIPS_VerilogHDL_Study_v1.0\min_sopc\openmips_min_sopc.v, 3260 , 2014-02-16
OpenMIPS_VerilogHDL_Study_v1.0\openmips模块连接关系图.vsd, 655872 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\rtl\cp0_reg.v, 6317 , 2014-02-14
OpenMIPS_VerilogHDL_Study_v1.0\rtl\ctrl.v, 3284 , 2014-03-02
OpenMIPS_VerilogHDL_Study_v1.0\rtl\defines.v, 7626 , 2014-02-13
OpenMIPS_VerilogHDL_Study_v1.0\rtl\div.v, 4942 , 2014-03-02
OpenMIPS_VerilogHDL_Study_v1.0\rtl\ex.v, 18376 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\rtl\ex_mem.v, 6118 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\rtl\hilo_reg.v, 2491 , 2014-02-10
OpenMIPS_VerilogHDL_Study_v1.0\rtl\id.v, 32225 , 2014-03-04
OpenMIPS_VerilogHDL_Study_v1.0\rtl\id_ex.v, 4948 , 2014-03-02
OpenMIPS_VerilogHDL_Study_v1.0\rtl\if_id.v, 2683 , 2014-02-16
OpenMIPS_VerilogHDL_Study_v1.0\rtl\LLbit_reg.v, 2394 , 2014-02-10
OpenMIPS_VerilogHDL_Study_v1.0\rtl\mem.v, 15001 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\rtl\mem_wb.v, 4850 , 2014-02-18
OpenMIPS_VerilogHDL_Study_v1.0\rtl\openmips.v, 16134 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\rtl\pc_reg.v, 2656 , 2014-03-02
OpenMIPS_VerilogHDL_Study_v1.0\rtl\regfile.v, 3386 , 2014-02-07
OpenMIPS_VerilogHDL_Study_v1.0\testbench\openmips_min_sopc_tb.v, 2330 , 2014-02-16
OpenMIPS_VerilogHDL_Study_v1.0\min_sopc, 0 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\rtl, 0 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0\testbench, 0 , 2014-03-05
OpenMIPS_VerilogHDL_Study_v1.0, 0 , 2014-03-05
说明.txt, 737 , 2019-04-28

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