uart_test

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 3311KB
Downloads: 0
Upload time: 2019-03-13 14:15:24
Uploader: 于旭阳
Description:   It is used to realize communication between upper computer and lower computer through RS232 protocol.

File list:
uart_test\clkdiv.bsf, 1775 , 2018-08-22
uart_test\clkdiv.v, 625 , 2018-08-22
uart_test\clkdiv.v.bak, 0 , 2018-08-22
uart_test\db\logic_util_heursitic.dat, 6908 , 2018-08-22
uart_test\db\prev_cmp_uart.qmsg, 85626 , 2018-08-22
uart_test\db\uart.(0).cnf.cdb, 5461 , 2018-08-22
uart_test\db\uart.(0).cnf.hdb, 1107 , 2018-08-22
uart_test\db\uart.(1).cnf.cdb, 1062 , 2018-08-22
uart_test\db\uart.(1).cnf.hdb, 590 , 2018-08-22
uart_test\db\uart.(2).cnf.cdb, 2687 , 2018-08-22
uart_test\db\uart.(2).cnf.hdb, 814 , 2018-08-22
uart_test\db\uart.(3).cnf.cdb, 2664 , 2018-08-22
uart_test\db\uart.(3).cnf.hdb, 928 , 2018-08-22
uart_test\db\uart.amm.cdb, 404 , 2018-08-22
uart_test\db\uart.asm.qmsg, 2240 , 2018-08-22
uart_test\db\uart.asm.rdb, 1332 , 2018-08-22
uart_test\db\uart.asm_labs.ddb, 10781 , 2018-08-22
uart_test\db\uart.cbx.xml, 86 , 2018-08-22
uart_test\db\uart.cmp.bpm, 544 , 2018-08-22
uart_test\db\uart.cmp.cdb, 23475 , 2018-08-22
uart_test\db\uart.cmp.hdb, 12950 , 2018-08-22
uart_test\db\uart.cmp.kpt, 199 , 2018-08-22
uart_test\db\uart.cmp.logdb, 8186 , 2018-08-22
uart_test\db\uart.cmp.rdb, 21102 , 2018-08-22
uart_test\db\uart.cmp_merge.kpt, 203 , 2018-08-22
uart_test\db\uart.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd, 746084 , 2018-08-22
uart_test\db\uart.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd, 739272 , 2018-08-22
uart_test\db\uart.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd, 740779 , 2018-08-22
uart_test\db\uart.db_info, 138 , 2018-08-22
uart_test\db\uart.eda.qmsg, 4773 , 2018-08-22
uart_test\db\uart.fit.qmsg, 22905 , 2018-08-22
uart_test\db\uart.hier_info, 2816 , 2018-08-22
uart_test\db\uart.hif, 2087 , 2018-08-22
uart_test\db\uart.idb.cdb, 3314 , 2018-08-22
uart_test\db\uart.lpc.html, 972 , 2018-08-22
uart_test\db\uart.lpc.rdb, 459 , 2018-08-22
uart_test\db\uart.lpc.txt, 1908 , 2018-08-22
uart_test\db\uart.map.bpm, 520 , 2018-08-22
uart_test\db\uart.map.cdb, 8340 , 2018-08-22
uart_test\db\uart.map.hdb, 12349 , 2018-08-22
uart_test\db\uart.map.kpt, 1291 , 2018-08-22
uart_test\db\uart.map.logdb, 4 , 2018-08-22
uart_test\db\uart.map.qmsg, 6430 , 2018-08-22
uart_test\db\uart.map_bb.cdb, 999 , 2018-08-22
uart_test\db\uart.map_bb.hdb, 8940 , 2018-08-22
uart_test\db\uart.map_bb.logdb, 4 , 2018-08-22
uart_test\db\uart.pre_map.cdb, 8540 , 2018-08-22
uart_test\db\uart.pre_map.hdb, 11357 , 2018-08-22
uart_test\db\uart.root_partition.map.reg_db.cdb, 186 , 2018-08-22
uart_test\db\uart.rtlv.hdb, 11333 , 2018-08-22
uart_test\db\uart.rtlv_sg.cdb, 8736 , 2018-08-22
uart_test\db\uart.rtlv_sg_swap.cdb, 854 , 2018-08-22
uart_test\db\uart.sgdiff.cdb, 8223 , 2018-08-22
uart_test\db\uart.sgdiff.hdb, 11438 , 2018-08-22
uart_test\db\uart.sld_design_entry.sci, 196 , 2018-12-03
uart_test\db\uart.sld_design_entry_dsc.sci, 197 , 2018-08-22
uart_test\db\uart.smart_action.txt, 6 , 2018-08-22
uart_test\db\uart.sta.qmsg, 48754 , 2018-08-22
uart_test\db\uart.sta.rdb, 28240 , 2018-08-22
uart_test\db\uart.sta_cmp.8_slow_1200mv_85c.tdb, 25853 , 2018-08-22
uart_test\db\uart.syn_hier_info, 0 , 2018-08-22
uart_test\db\uart.tiscmp.fastest_slow_1200mv_0c.ddb, 120698 , 2018-08-22
uart_test\db\uart.tiscmp.fastest_slow_1200mv_85c.ddb, 120704 , 2018-08-22
uart_test\db\uart.tiscmp.fast_1200mv_0c.ddb, 177227 , 2018-08-22
uart_test\db\uart.tiscmp.slow_1200mv_0c.ddb, 178086 , 2018-08-22
uart_test\db\uart.tiscmp.slow_1200mv_85c.ddb, 178185 , 2018-08-22
uart_test\db\uart.tis_db_list.ddb, 231 , 2018-08-22
uart_test\db\uart.tmw_info, 310 , 2018-12-03
uart_test\incremental_db\compiled_partitions\uart.db_info, 138 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.cmp.cdb, 10737 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.cmp.dfp, 33 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.cmp.hdb, 12598 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.cmp.kpt, 201 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.cmp.logdb, 4 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.cmp.rcfdb, 10563 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.cdb, 8145 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.dpi, 939 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.cdb, 605 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.hb_info, 46 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.hdb, 12046 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.hbdb.sig, 31 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.hdb, 12445 , 2018-08-22
uart_test\incremental_db\compiled_partitions\uart.root_partition.map.kpt, 1299 , 2018-08-22
uart_test\incremental_db\README, 653 , 2018-08-22
uart_test\simulation\modelsim\uart.sft, 322 , 2018-08-22
uart_test\simulation\modelsim\uart.vo, 87098 , 2018-08-22
uart_test\simulation\modelsim\uart_8_1200mv_0c_slow.vo, 87115 , 2018-08-22
uart_test\simulation\modelsim\uart_8_1200mv_0c_v_slow.sdo, 74260 , 2018-08-22
uart_test\simulation\modelsim\uart_8_1200mv_85c_slow.vo, 87116 , 2018-08-22
uart_test\simulation\modelsim\uart_8_1200mv_85c_v_slow.sdo, 74363 , 2018-08-22
uart_test\simulation\modelsim\uart_min_1200mv_0c_fast.vo, 87117 , 2018-08-22
uart_test\simulation\modelsim\uart_min_1200mv_0c_v_fast.sdo, 72721 , 2018-08-22
uart_test\simulation\modelsim\uart_modelsim.xrf, 9949 , 2018-08-22
uart_test\simulation\modelsim\uart_v.sdo, 74363 , 2018-08-22
uart_test\testuart.bsf, 1977 , 2018-08-22
uart_test\testuart.v, 633 , 2018-08-22
uart_test\testuart.v.bak, 0 , 2018-08-22
uart_test\uart.asm.rpt, 6823 , 2018-08-22
uart_test\uart.bdf, 6470 , 2018-08-22
uart_test\uart.bsf, 2465 , 2018-08-22

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