整个工程代码

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 11KB
Downloads: 9
Upload time: 2019-01-21 17:21:27
Uploader: 明月心447
Description:   Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.

File list:
整个工程代码\FIFO_PLL.v, 6146 , 2018-07-13
整个工程代码\FIFO_PLL_inst.v, 164 , 2018-07-13
整个工程代码\sdram_decode.v, 1396 , 2018-07-15
整个工程代码\sdram_init.v, 2146 , 2018-07-14
整个工程代码\sdram_read.v, 7258 , 2018-07-17
整个工程代码\sdram_ref.v, 2059 , 2018-07-14
整个工程代码\sdram_top.v, 5170 , 2018-07-16
整个工程代码\sdram_write.v, 6660 , 2018-07-17
整个工程代码\top.v, 3797 , 2019-01-14
整个工程代码\top.v~, 3796 , 2018-07-16
整个工程代码\uart_rx.v, 1922 , 2018-07-15
整个工程代码\uart_tx.v, 2385 , 2018-07-15
整个工程代码, 0 , 2019-01-14

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