sdram_cntrl_verilog_for_DE0

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 283KB
Downloads: 0
Upload time: 2019-01-15 02:37:23
Uploader: sgot
Description:   My sdram verilog controller for DE0

File list:
greybox_tmp, 0 , 2019-01-15
greybox_tmp\cbx_args.txt, 1576 , 2019-01-15
model, 0 , 2019-01-15
model\42s16160.v, 40138 , 2019-01-15
output_files, 0 , 2019-01-15
output_files\greybox_tmp, 0 , 2019-01-15
output_files\greybox_tmp\cbx_args.txt, 1576 , 2019-01-15
output_files\pll.qip, 0 , 2019-01-15
output_files\sdram_cntr.jdi, 229 , 2019-01-15
output_files\sdram_cntr.pin, 32794 , 2019-01-15
output_files\sdram_cntr.sof, 703961 , 2019-01-15
simulation, 0 , 2019-01-15
simulation\modelsim, 0 , 2019-01-15
simulation\modelsim\42s16160.v, 40138 , 2019-01-15
simulation\modelsim\modelsim.ini, 11137 , 2019-01-15
simulation\modelsim\sdram_cntr.sft, 365 , 2019-01-15
simulation\modelsim\sdram_cntr.vo, 420278 , 2019-01-15
simulation\modelsim\sdram_cntr_6_1200mv_0c_slow.vo, 420295 , 2019-01-15
simulation\modelsim\sdram_cntr_6_1200mv_0c_v_slow.sdo, 305811 , 2019-01-15
simulation\modelsim\sdram_cntr_6_1200mv_85c_slow.vo, 420296 , 2019-01-15
simulation\modelsim\sdram_cntr_6_1200mv_85c_v_slow.sdo, 306031 , 2019-01-15
simulation\modelsim\sdram_cntr_min_1200mv_0c_fast.vo, 420297 , 2019-01-15
simulation\modelsim\sdram_cntr_min_1200mv_0c_v_fast.sdo, 300096 , 2019-01-15
simulation\modelsim\sdram_cntr_v.sdo, 306031 , 2019-01-15
simulation\modelsim\top.vt, 5415 , 2019-01-15
pll.ppf, 495 , 2019-01-15
pll.qip, 351 , 2019-01-15
pll.v, 17417 , 2019-01-15
pll_bb.v, 13168 , 2019-01-15
PLLJ_PLLSPE_INFO.txt, 119 , 2019-01-15
README.md, 80 , 2019-01-15
sdram_cntr.qpf, 1283 , 2019-01-15
sdram_cntr.qsf, 11406 , 2019-01-15
sdram_cntr.sdc, 874 , 2019-01-15
sdram_cntr.v, 16905 , 2019-01-15
top.v, 8465 , 2019-01-15

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