vga

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 5810KB
Downloads: 1
Upload time: 2017-08-28 22:20:11
Uploader: AYEA
Description:   VGA interface on the program, simulation success, for learning to use

File list:
vga
vga\PLLJ_PLLSPE_INFO.txt
vga\db
vga\db\logic_util_heursitic.dat
vga\db\pll_altpll.v
vga\db\prev_cmp_vga_test.qmsg
vga\db\vga_test.asm.qmsg
vga\db\vga_test.asm.rdb
vga\db\vga_test.asm_labs.ddb
vga\db\vga_test.cbx.xml
vga\db\vga_test.cmp.bpm
vga\db\vga_test.cmp.cdb
vga\db\vga_test.cmp.hdb
vga\db\vga_test.cmp.idb
vga\db\vga_test.cmp.kpt
vga\db\vga_test.cmp.logdb
vga\db\vga_test.cmp.rdb
vga\db\vga_test.cmp_merge.kpt
vga\db\vga_test.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
vga\db\vga_test.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
vga\db\vga_test.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
vga\db\vga_test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
vga\db\vga_test.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
vga\db\vga_test.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
vga\db\vga_test.db_info
vga\db\vga_test.fit.qmsg
vga\db\vga_test.hier_info
vga\db\vga_test.hif
vga\db\vga_test.ipinfo
vga\db\vga_test.lpc.html
vga\db\vga_test.lpc.rdb
vga\db\vga_test.lpc.txt
vga\db\vga_test.map.bpm
vga\db\vga_test.map.cdb
vga\db\vga_test.map.hdb
vga\db\vga_test.map.kpt
vga\db\vga_test.map.logdb
vga\db\vga_test.map.qmsg
vga\db\vga_test.map.rdb
vga\db\vga_test.map_bb.cdb
vga\db\vga_test.map_bb.hdb
vga\db\vga_test.map_bb.logdb
vga\db\vga_test.pplq.rdb
vga\db\vga_test.pre_map.cdb
vga\db\vga_test.pre_map.hdb
vga\db\vga_test.qns
vga\db\vga_test.root_partition.map.reg_db.cdb
vga\db\vga_test.routing.rdb
vga\db\vga_test.rtlv.hdb
vga\db\vga_test.rtlv_sg.cdb
vga\db\vga_test.rtlv_sg_swap.cdb
vga\db\vga_test.sas
vga\db\vga_test.sgdiff.cdb
vga\db\vga_test.sgdiff.hdb
vga\db\vga_test.sld_design_entry.sci
vga\db\vga_test.sld_design_entry_dsc.sci
vga\db\vga_test.smart_action.txt
vga\db\vga_test.sta.qmsg
vga\db\vga_test.sta.rdb
vga\db\vga_test.sta_cmp.8_slow_1200mv_85c.tdb
vga\db\vga_test.syn_hier_info
vga\db\vga_test.tis_db_list.ddb
vga\db\vga_test.tiscmp.fast_1200mv_0c.ddb
vga\db\vga_test.tiscmp.fastest_slow_1200mv_0c.ddb
vga\db\vga_test.tiscmp.fastest_slow_1200mv_85c.ddb
vga\db\vga_test.tiscmp.slow_1200mv_0c.ddb
vga\db\vga_test.tiscmp.slow_1200mv_85c.ddb
vga\db\vga_test.tmw_info
vga\db\vga_test.vpr.ammdb
vga\incremental_db
vga\incremental_db\README
vga\incremental_db\compiled_partitions
vga\incremental_db\compiled_partitions\vga_test.db_info
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.ammdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.cdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.dfp
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.hdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.kpt
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.logdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.cmp.rcfdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.cdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.dpi
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.hbdb.cdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.hbdb.hb_info
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.hbdb.hdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.hbdb.sig
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.hdb
vga\incremental_db\compiled_partitions\vga_test.root_partition.map.kpt
vga\output_files
vga\output_files\vga_test.asm.rpt
vga\output_files\vga_test.cdf
vga\output_files\vga_test.done
vga\output_files\vga_test.fit.rpt
vga\output_files\vga_test.fit.smsg
vga\output_files\vga_test.fit.summary
vga\output_files\vga_test.flow.rpt
vga\output_files\vga_test.jdi
vga\output_files\vga_test.map.rpt
vga\output_files\vga_test.map.summary
vga\output_files\vga_test.pin

Download users:

Relate files:

Comment: Add Comment

Favorite users: