sdram

Directory: VHDL-FPGA-Verilog
Plat: Verilog
Size: 8752KB
Downloads: 2
Upload time: 2017-08-28 22:17:48
Uploader: AYEA
Description:   SDRAM program source code, simulation success, available for learning to use

File list:
sdram
sdram\PLLJ_PLLSPE_INFO.txt
sdram\db
sdram\db\altsyncram_2124.tdf
sdram\db\altsyncram_6124.tdf
sdram\db\altsyncram_7124.tdf
sdram\db\altsyncram_g124.tdf
sdram\db\altsyncram_i124.tdf
sdram\db\cmpr_ngc.tdf
sdram\db\cmpr_rgc.tdf
sdram\db\cmpr_sgc.tdf
sdram\db\cntr_23j.tdf
sdram\db\cntr_fgi.tdf
sdram\db\cntr_ggi.tdf
sdram\db\cntr_hgi.tdf
sdram\db\cntr_igi.tdf
sdram\db\cntr_m9j.tdf
sdram\db\cntr_mgi.tdf
sdram\db\cntr_o9j.tdf
sdram\db\decode_dvf.tdf
sdram\db\logic_util_heursitic.dat
sdram\db\mux_tsc.tdf
sdram\db\mux_vsc.tdf
sdram\db\prev_cmp_sdram_test.qmsg
sdram\db\sdram_pll_altpll.v
sdram\db\sdram_test.asm.qmsg
sdram\db\sdram_test.asm.rdb
sdram\db\sdram_test.asm_labs.ddb
sdram\db\sdram_test.autoh_e40e1.map.reg_db.cdb
sdram\db\sdram_test.autos_3e921.map.reg_db.cdb
sdram\db\sdram_test.cbx.xml
sdram\db\sdram_test.cmp.bpm
sdram\db\sdram_test.cmp.cdb
sdram\db\sdram_test.cmp.hdb
sdram\db\sdram_test.cmp.idb
sdram\db\sdram_test.cmp.kpt
sdram\db\sdram_test.cmp.logdb
sdram\db\sdram_test.cmp.rdb
sdram\db\sdram_test.cmp_merge.kpt
sdram\db\sdram_test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
sdram\db\sdram_test.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
sdram\db\sdram_test.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
sdram\db\sdram_test.db_info
sdram\db\sdram_test.eda.qmsg
sdram\db\sdram_test.fit.qmsg
sdram\db\sdram_test.hier_info
sdram\db\sdram_test.hif
sdram\db\sdram_test.ipinfo
sdram\db\sdram_test.lpc.html
sdram\db\sdram_test.lpc.rdb
sdram\db\sdram_test.lpc.txt
sdram\db\sdram_test.map.bpm
sdram\db\sdram_test.map.cdb
sdram\db\sdram_test.map.hdb
sdram\db\sdram_test.map.kpt
sdram\db\sdram_test.map.logdb
sdram\db\sdram_test.map.qmsg
sdram\db\sdram_test.map.rdb
sdram\db\sdram_test.map_bb.cdb
sdram\db\sdram_test.map_bb.hdb
sdram\db\sdram_test.map_bb.logdb
sdram\db\sdram_test.pplq.rdb
sdram\db\sdram_test.pre_map.cdb
sdram\db\sdram_test.pre_map.hdb
sdram\db\sdram_test.qns
sdram\db\sdram_test.root_partition.map.reg_db.cdb
sdram\db\sdram_test.routing.rdb
sdram\db\sdram_test.rtlv.hdb
sdram\db\sdram_test.rtlv_sg.cdb
sdram\db\sdram_test.rtlv_sg_swap.cdb
sdram\db\sdram_test.sas
sdram\db\sdram_test.sgdiff.cdb
sdram\db\sdram_test.sgdiff.hdb
sdram\db\sdram_test.sld_design_entry.sci
sdram\db\sdram_test.sld_design_entry_dsc.sci
sdram\db\sdram_test.smart_action.txt
sdram\db\sdram_test.smp_dump.txt
sdram\db\sdram_test.sta.qmsg
sdram\db\sdram_test.sta.rdb
sdram\db\sdram_test.sta_cmp.8_slow_1200mv_85c.tdb
sdram\db\sdram_test.syn_hier_info
sdram\db\sdram_test.tis_db_list.ddb
sdram\db\sdram_test.tiscmp.fast_1200mv_0c.ddb
sdram\db\sdram_test.tiscmp.fastest_slow_1200mv_0c.ddb
sdram\db\sdram_test.tiscmp.fastest_slow_1200mv_85c.ddb
sdram\db\sdram_test.tiscmp.slow_1200mv_0c.ddb
sdram\db\sdram_test.tiscmp.slow_1200mv_85c.ddb
sdram\db\sdram_test.vpr.ammdb
sdram\incremental_db
sdram\incremental_db\README
sdram\incremental_db\compiled_partitions
sdram\incremental_db\compiled_partitions\sdram_test.autoh_e40e1.map.cdb
sdram\incremental_db\compiled_partitions\sdram_test.autoh_e40e1.map.dpi
sdram\incremental_db\compiled_partitions\sdram_test.autoh_e40e1.map.hdb
sdram\incremental_db\compiled_partitions\sdram_test.autoh_e40e1.map.kpt
sdram\incremental_db\compiled_partitions\sdram_test.autoh_e40e1.map.logdb
sdram\incremental_db\compiled_partitions\sdram_test.autos_3e921.map.cdb
sdram\incremental_db\compiled_partitions\sdram_test.autos_3e921.map.dpi
sdram\incremental_db\compiled_partitions\sdram_test.autos_3e921.map.hdb
sdram\incremental_db\compiled_partitions\sdram_test.autos_3e921.map.kpt

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