uart(Verilog)

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 11KB
Downloads: 2
Upload time: 2016-06-25 19:18:07
Uploader: 大翔W
Description:   uart test code

File list:
uart 源码 (Verilog)
...................\address_decode.v,1491,2001-09-11
...................\clock_divider.v,2123,2001-09-11
...................\control_operation.v,3265,2001-09-11
...................\cpu_interface.v,1648,2001-09-11
...................\serial_interface.v,4089,2001-09-11
...................\status_registers.v,1894,2001-09-11
...................\tester.v,6428,2001-09-11
...................\uart_tb.v,1286,2001-09-11
...................\uart_top.v,3018,2001-09-11
...................\xmit_rcv_control.v,12293,2001-09-11

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