Directory: VHDL-FPGA-Verilog
Plat: PDF
Size: 918KB
Downloads: 2
Upload time: 2015-10-28 18:05:28
Uploader: ANU MOHAN
Description:   This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead.

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