frequency-agility

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 2412KB
Downloads: 21
Upload time: 2015-10-15 10:37:54
Uploader: 0516咪咪
Description:   The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB

File list:
捷变频
......\skip.m,414,2015-01-05
......\捷变频.rar,2605699,2015-10-15

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