video_center_scan_scaler_alpha_blend

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 8283KB
Downloads: 30
Upload time: 2015-06-20 13:20:50
Uploader: 冰凝
Description:   scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discription

File list:
ddr_test.tcl,16572,2015-03-17
fifo_2048_30.qip,0,2015-03-20
fifo_256_64.qip,0,2015-03-20
greybox_tmp
...........\cbx_args.txt,396,2015-03-25
output_files
............\fifo_2048_30.qip,0,2015-03-19
............\fifo_256_64.qip,0,2015-03-19
............\greybox_tmp
............\...........\cbx_args.txt,398,2015-03-20
............\output_files
............\stp1.stp,150839,2015-03-24
............\stp1_auto_stripped.stp,150839,2015-03-25
............\sys_pll.qip,0,2014-12-24
............\top.asm.rpt,8386,2015-03-31
............\top.cdf,339,2015-03-31
............\top.done,26,2015-03-31
............\top.eda.rpt,8764,2015-03-31
............\top.fit.rpt,2969679,2015-03-31
............\top.fit.smsg,567,2015-03-31
............\top.fit.summary,632,2015-03-31
............\top.flow.rpt,13512,2015-03-31
............\top.jdi,222,2015-03-31
............\top.map.rpt,4282364,2015-03-31
............\top.map.smsg,476,2015-03-31
............\top.map.summary,484,2015-03-31
............\top.pin,57903,2015-03-31
............\top.pof,2097374,2015-03-31
............\top.sof,503261,2015-03-31
............\top.sta.rpt,5656382,2015-03-31
............\top.sta.summary,7054,2015-03-31
PLLJ_PLLSPE_INFO.txt,133,2014-12-18
serv_req_info.txt,492,2014-12-10
simulation
..........\modelsim
..........\........\top.sft,316,2015-03-31
..........\........\top.vo,21845426,2015-03-31
..........\........\top_8_1200mv_0c_slow.vo,21845443,2015-03-31
..........\........\top_8_1200mv_0c_v_slow.sdo,10644057,2015-03-31
..........\........\top_8_1200mv_85c_slow.vo,21845444,2015-03-31
..........\........\top_8_1200mv_85c_v_slow.sdo,10740706,2015-03-31
..........\........\top_min_1200mv_0c_fast.vo,21845445,2015-03-31
..........\........\top_min_1200mv_0c_v_fast.sdo,10535781,2015-03-31
..........\........\top_modelsim.xrf,3641611,2015-03-31
..........\........\top_v.sdo,10740706,2015-03-31
sram_test.out.sdc,4973,2014-12-10
sram_test.qws,613,2014-12-18
src
...\alpha_blend.v,4240,2015-03-31
...\alpha_blend.v.bak,3843,2015-03-25
...\circle_scan.v,9844,2015-03-17
...\circle_scan.v.bak,9844,2014-12-23
...\common_std_logic_vector_delay.vhd,1807,2014-07-26
...\ddr_top
...\.......\27Mhz-133Mhz.txt,0,2014-11-11
...\.......\alt_mem_phy_defines.v,5281,2014-11-11
...\.......\alt_mem_phy_sequencer.vhd,634688,2014-11-11
...\.......\auk_ddr_hp_controller.ocp,488,2014-11-11
...\.......\auk_ddr_hp_controller.vhd,296944,2014-11-11
...\.......\ddr2.html,4824,2014-11-11
...\.......\ddr2.ppf,18092,2014-11-11
...\.......\ddr2.qip,1038,2014-11-11
...\.......\ddr2.v,20778,2014-11-11
...\.......\ddr2_advisor.ipa,41851,2014-11-11
...\.......\ddr2_auk_ddr_hp_controller_wrapper.v,13058,2014-11-11
...\.......\ddr2_bb.v,3037,2014-11-11
...\.......\ddr2_controller_phy.v,16714,2014-11-11
...\.......\ddr2_example_driver.v,30640,2014-11-11
...\.......\ddr2_example_top.sdc,162,2014-11-11
...\.......\ddr2_example_top.v,6676,2014-11-11
...\.......\ddr2_example_top.v.tmp,6676,2014-11-11
...\.......\ddr2_example_top.v.tmp2,6676,2014-11-11
...\.......\ddr2_example_top_1.v,6676,2014-11-11
...\.......\ddr2_ex_lfsr8.v,1393,2014-11-11
...\.......\ddr2_phy.html,9074,2014-11-11
...\.......\ddr2_phy.qip,1231,2014-11-11
...\.......\ddr2_phy.v,29764,2014-11-11
...\.......\ddr2_phy_alt_mem_phy.v,169103,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_pll.bsf,6538,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_pll.ppf,1117,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_pll.qip,516,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_pll.v,22196,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_pll.v_.bak,16623,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_pll_bb.v,17219,2014-11-11
...\.......\ddr2_phy_alt_mem_phy_sequencer_wrapper.v,14836,2014-11-11
...\.......\ddr2_phy_bb.v,6679,2014-11-11
...\.......\ddr2_phy_ddr_pins.tcl,34220,2014-11-11
...\.......\ddr2_phy_ddr_timing.sdc,29962,2014-11-11
...\.......\ddr2_phy_report_timing.tcl,19401,2014-11-11
...\.......\ddr2_phy_simgen_init.txt,209,2014-11-11
...\.......\ddr2_pin_assignments.tcl,16593,2014-11-11
...\.......\testbench
...\.......\.........\ddr2_example_top_tb.v,15396,2014-11-11
...\.......\.........\ddr2_example_top_tb.v.tmp,15396,2014-11-11
...\.......\.........\ddr2_example_top_tb.v.tmp2,15396,2014-11-11
...\.......\.........\ddr2_example_top_tb_1.v,15396,2014-11-11
...\.......\.........\ddr2_mem_model.v,20044,2014-11-11
...\dp_ram.v,1313,2014-08-18
...\ip
...\..\ddio_out.v,4345,2013-09-28

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