DE2_TV

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 210KB
Downloads: 10
Upload time: 2014-11-10 18:22:46
Uploader: chenxin
Description:   This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The TV_to_VGA block consists of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444, YCrCb to RGB, and VGA Controller.

File list:
DE2_TV
......\DE2_TV.done,26,2012-08-24
......\DE2_TV.fit.smsg,567,2012-08-24
......\DE2_TV.fit.summary,629,2012-08-24
......\DE2_TV.jdi,319,2012-08-24
......\DE2_TV.map.summary,485,2012-08-24
......\DE2_TV.pin,78708,2012-08-24
......\DE2_TV.pof,2097362,2012-08-24
......\DE2_TV.qpf,1266,2012-08-24
......\DE2_TV.qsf,28129,2012-08-24
......\DE2_TV.sdc,1747,2012-08-24
......\DE2_TV.sof,841113,2012-08-24
......\DE2_TV.sta.summary,3701,2012-08-24
......\DE2_TV.v,20994,2012-08-24
......\DE2_TV_assignment_defaults.qdf,51988,2012-08-24
......\demo_batch
......\..........\DE2_TV.sof,841113,2012-08-24
......\..........\test.bat,93,2012-08-24
......\DIV.qip,0,2012-08-24
......\greybox_tmp
......\...........\cbx_args.txt,236,2012-08-24
......\Line_Buffer.qip,0,2012-08-24
......\MAC_3.qip,0,2012-08-24
......\Sdram_Control_4Port
......\...................\command.v,17066,2012-08-24
......\...................\control_interface.v,5812,2012-08-24
......\...................\greybox_tmp
......\...................\...........\cbx_args.txt,1531,2012-08-24
......\...................\Sdram_Control_4Port.v,14793,2012-08-24
......\...................\Sdram_Params.h,1542,2012-08-24
......\...................\Sdram_PLL.ppf,499,2012-08-24
......\...................\Sdram_PLL.qip,280,2012-08-24
......\...................\Sdram_PLL.v,17412,2012-08-24
......\...................\Sdram_RD_FIFO.qip,194,2012-08-24
......\...................\Sdram_RD_FIFO.v,7650,2012-08-24
......\...................\Sdram_WR_FIFO.qip,194,2012-08-24
......\...................\Sdram_WR_FIFO.v,7650,2012-08-24
......\...................\sdr_data_path.v,909,2012-08-24
......\Sdram_PLL.qip,0,2012-08-24
......\Sdram_WR_FIFO.qip,0,2012-08-24
......\v
......\.\AUDIO_DAC.v,8754,2012-08-24
......\.\DIV.v,4635,2012-08-24
......\.\I2C_AV_Config.v,5594,2012-08-24
......\.\I2C_Controller.v,3871,2012-08-24
......\.\ITU_656_Decoder.v,2813,2012-08-24
......\.\Line_Buffer.v,4768,2012-08-24
......\.\MAC_3.v,15476,2012-08-24
......\.\PLL.v,14609,2012-08-24
......\.\Reset_Delay.v,497,2012-08-24
......\.\SEG7_LUT.v,705,2012-08-24
......\.\SEG7_LUT_8.v,458,2012-08-24
......\.\TD_Detect.v,1213,2012-08-24
......\.\TP_RAM.v,8078,2012-08-24
......\.\VGA_Ctrl.v,2818,2012-08-24
......\.\YCbCr2RGB.v,4129,2012-08-24
......\.\YUV422_to_444.v,734,2012-08-24

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