IO

Directory: VHDL-FPGA-Verilog
Plat: C/C++
Size: 24KB
Downloads: 1
Upload time: 2014-10-24 16:09:16
Uploader: ohohohoh
Description:   Through experiments to understand the I/O port is used as input and output, CPU to I/O port operation

File list:
test1
.....\STARTUP.A51,6376,2009-05-07
.....\STARTUP.LST,14061,2012-11-09
.....\STARTUP.OBJ,749,2012-11-09
.....\t1.c,1010,2012-11-11
.....\t1.LST,2881,2012-11-11
.....\t1.OBJ,4411,2012-11-11
.....\t1.__i,32,2012-11-11
.....\test1,4490,2012-11-11
.....\test1.lnp,40,2012-11-11
.....\test1.M51,7201,2012-11-11
.....\test1.plg,161,2012-11-19
.....\test1.uvopt,56003,2012-11-17
.....\test1.uvproj,13393,2012-11-09
.....\test1_uvopt.bak,56978,2012-11-11
.....\test1_uvproj.bak,0,2012-11-09

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