powerlink

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 2869KB
Downloads: 68
Upload time: 2014-04-28 10:55:45
Uploader: wholered
Description:   powerlink slave VHDL sourcecode,which is based on Xilinx platform.

File list:
powerlink
.........\pcores
.........\......\axi_powerlink_v0_28_a
.........\......\.....................\data
.........\......\.....................\....\axi_powerlink_v2_1_0.mdd,2554,2013-11-09
.........\......\.....................\....\axi_powerlink_v2_1_0.mpd,35799,2013-11-09
.........\......\.....................\....\axi_powerlink_v2_1_0.mui,25421,2013-11-09
.........\......\.....................\....\axi_powerlink_v2_1_0.pao,4456,2013-11-09
.........\......\.....................\....\axi_powerlink_v2_1_0.tcl,40201,2013-11-09
.........\......\.....................\doc
.........\......\.....................\...\01_POWERLINK-IP-Core_Xilinx.pdf,349253,2013-11-09
.........\......\.....................\...\02_POWERLINK-IP-Core_Generic.pdf,1004357,2013-11-09
.........\......\.....................\...\03_OpenMAC.pdf,310806,2013-11-09
.........\......\.....................\hdl
.........\......\.....................\...\vhdl
.........\......\.....................\...\....\axi_powerlink.vhd,84322,2013-11-09
.........\......\.....................\...\....\lib
.........\......\.....................\...\....\...\addr_decoder.vhd,3144,2013-11-09
.........\......\.....................\...\....\...\edgedet.vhd,3158,2013-11-09
.........\......\.....................\...\....\...\memMap.vhd,3161,2013-11-09
.........\......\.....................\...\....\...\req_ack.vhd,3512,2013-11-09
.........\......\.....................\...\....\...\slow2fastSync.vhd,3726,2013-11-09
.........\......\.....................\...\....\...\sync.vhd,2976,2013-11-09
.........\......\.....................\...\....\openFILTER.vhd,11093,2013-11-09
.........\......\.....................\...\....\openHUB.vhd,6522,2013-11-09
.........\......\.....................\...\....\openMAC.vhd,51955,2013-11-09
.........\......\.....................\...\....\openMAC_16to32conv.vhd,6853,2013-11-09
.........\......\.....................\...\....\openMAC_cmp.vhd,4584,2013-11-09
.........\......\.....................\...\....\openMAC_DMAFifo_Xilinx
.........\......\.....................\...\....\......................\async_fifo_ctrl.vhd,5664,2013-11-09
.........\......\.....................\...\....\......................\fifo_read.vhd,5197,2013-11-09
.........\......\.....................\...\....\......................\fifo_write.vhd,5192,2013-11-09
.........\......\.....................\...\....\......................\n_synchronizer.vhd,3499,2013-11-09
.........\......\.....................\...\....\openMAC_DMAFifo_Xilinx.vhd,6421,2013-11-09
.........\......\.....................\...\....\openMAC_DMAmaster
.........\......\.....................\...\....\.................\dma_handler.vhd,8114,2013-11-09
.........\......\.....................\...\....\.................\ipif_master_handler.vhd,11074,2013-11-09
.........\......\.....................\...\....\.................\master_handler.vhd,14784,2013-11-09
.........\......\.....................\...\....\openMAC_DMAmaster.vhd,22013,2013-11-09
.........\......\.....................\...\....\openMAC_DPR_Altera_qsys.vhd,9499,2013-11-09
.........\......\.....................\...\....\openMAC_DPR_Xilinx.vhd,11468,2013-11-09
.........\......\.....................\...\....\openMAC_Ethernet.vhd,39365,2013-11-09
.........\......\.....................\...\....\openMAC_phyAct.vhd,4237,2013-11-09
.........\......\.....................\...\....\openMAC_PHYMI.vhd,5745,2013-11-09
.........\......\.....................\...\....\openMAC_rmii2mii.vhd,9282,2013-11-09
.........\......\.....................\...\....\pdi.vhd,53242,2013-11-09
.........\......\.....................\...\....\pdi_apIrqGen.vhd,4783,2013-11-09
.........\......\.....................\...\....\pdi_controlStatusReg.vhd,20196,2013-11-09
.........\......\.....................\...\....\pdi_dpr_Xilinx.vhd,3605,2013-11-09
.........\......\.....................\...\....\pdi_event.vhd,7403,2013-11-09
.........\......\.....................\...\....\pdi_led.vhd,3782,2013-11-09
.........\......\.....................\...\....\pdi_par.vhd,13053,2013-11-09
.........\......\.....................\...\....\pdi_simpleReg.vhd,3791,2013-11-09
.........\......\.....................\...\....\pdi_spi.vhd,10898,2013-11-09
.........\......\.....................\...\....\pdi_tripleVBufLogic.vhd,12178,2013-11-09
.........\......\.....................\...\....\portio.vhd,8031,2013-11-09
.........\......\.....................\...\....\portio_cnt.vhd,3422,2013-11-09
.........\......\.....................\...\....\powerlink.vhd,34686,2013-11-09
.........\......\.....................\...\....\spi.vhd,5952,2013-11-09
.........\......\.....................\...\....\spi_sreg.vhd,1071,2013-11-09
.........\......\.....................\revision.txt,4587,2013-11-09
.........\......\plb_powerlink_v0_28_a
.........\......\.....................\data
.........\......\.....................\....\plb_powerlink_v2_1_0.mdd,2501,2013-11-09
.........\......\.....................\....\plb_powerlink_v2_1_0.mpd,43020,2013-11-09
.........\......\.....................\....\plb_powerlink_v2_1_0.mui,26025,2013-11-09
.........\......\.....................\....\plb_powerlink_v2_1_0.pao,4492,2013-11-09
.........\......\.....................\....\plb_powerlink_v2_1_0.tcl,39009,2013-11-09
.........\......\.....................\doc
.........\......\.....................\...\01_POWERLINK-IP-Core_Xilinx.pdf,349253,2013-11-09
.........\......\.....................\...\02_POWERLINK-IP-Core_Generic.pdf,1004357,2013-11-09
.........\......\.....................\...\03_OpenMAC.pdf,310806,2013-11-09
.........\......\.....................\hdl
.........\......\.....................\...\vhdl
.........\......\.....................\...\....\lib
.........\......\.....................\...\....\...\addr_decoder.vhd,3144,2013-11-09
.........\......\.....................\...\....\...\edgedet.vhd,3158,2013-11-09
.........\......\.....................\...\....\...\memMap.vhd,3161,2013-11-09
.........\......\.....................\...\....\...\req_ack.vhd,3512,2013-11-09
.........\......\.....................\...\....\...\slow2fastSync.vhd,3726,2013-11-09
.........\......\.....................\...\....\...\sync.vhd,2976,2013-11-09
.........\......\.....................\...\....\openFILTER.vhd,11093,2013-11-09
.........\......\.....................\...\....\openHUB.vhd,6522,2013-11-09
.........\......\.....................\...\....\openMAC.vhd,51955,2013-11-09
.........\......\.....................\...\....\openMAC_16to32conv.vhd,6853,2013-11-09
.........\......\.....................\...\....\openMAC_cmp.vhd,4584,2013-11-09
.........\......\.....................\...\....\openMAC_DMAFifo_Xilinx
.........\......\.....................\...\....\......................\async_fifo_ctrl.vhd,5664,2013-11-09
.........\......\.....................\...\....\......................\fifo_read.vhd,5197,2013-11-09
.........\......\.....................\...\....\......................\fifo_write.vhd,5192,2013-11-09
.........\......\.....................\...\....\......................\n_synchronizer.vhd,3499,2013-11-09
.........\......\.....................\...\....\openMAC_DMAFifo_Xilinx.vhd,6421,2013-11-09
.........\......\.....................\...\....\openMAC_DMAmaster
.........\......\.....................\...\....\.................\dma_handler.vhd,8114,2013-11-09
.........\......\.....................\...\....\.................\ipif_master_handler.vhd,11074,2013-11-09
.........\......\.....................\...\....\.................\master_handler.vhd,14784,2013-11-09
.........\......\.....................\...\....\openMAC_DMAmaster.vhd,22013,2013-11-09
.........\......\.....................\...\....\openMAC_DPR_Xilinx.vhd,11468,2013-11-09
.........\......\.....................\...\....\openMAC_Ethernet.vhd,39365,2013-11-09
.........\......\.....................\...\....\openMAC_phyAct.vhd,4237,2013-11-09

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