UART

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 423KB
Downloads: 33
Upload time: 2012-04-12 19:11:56
Uploader: panzdguof
Description:   verilog to write the serial program, its function is completely the right, with the project file

File list:
UART
....\Project
....\.......\Fusion_UART
....\.......\...........\component
....\.......\...........\constraint
....\.......\...........\..........\uart_test.pdc,824,2007-10-15
....\.......\...........\coreconsole
....\.......\...........\designer
....\.......\...........\........\impl1
....\.......\...........\........\.....\designer.log,8996,2007-10-15
....\.......\...........\........\.....\designer_genhdl.log,7810,2007-08-19
....\.......\...........\........\.....\simulation
....\.......\...........\........\.....\uart_test.adb,189952,2007-10-15
....\.......\...........\........\.....\uart_test.dtf
....\.......\...........\........\.....\.............\verify.log,233,2007-10-15
....\.......\...........\........\.....\uart_test.ide_des,667,2007-10-15
....\.......\...........\........\.....\uart_test.pdb,84480,2007-10-15
....\.......\...........\........\.....\uart_test.pdb.depends,0,2007-10-15
....\.......\...........\........\.....\uart_test.stp,62204,2007-10-15
....\.......\...........\........\.....\uart_test.tcl,174,2007-10-15
....\.......\...........\........\.....\uart_test_ba.sdf,129603,2007-10-15
....\.......\...........\........\.....\uart_test_ba.v,48030,2007-10-15
....\.......\...........\hdl
....\.......\...........\...\hdlsynchk.tcl,124,2007-12-11
....\.......\...........\...\rec.v,2572,2007-07-31
....\.......\...........\...\send.v,2251,2007-07-31
....\.......\...........\...\uart_test.v,1385,2011-04-07
....\.......\...........\phy_synthesis
....\.......\...........\simulation
....\.......\...........\..........\meminit.dat,2816,2007-10-15
....\.......\...........\..........\modelsim.ini,264,2011-04-07
....\.......\...........\..........\modelsim.ini.sav,222,2007-12-17
....\.......\...........\smartgen
....\.......\...........\........\smartgen.aws,364,2011-04-07
....\.......\...........\stimulus
....\.......\...........\........\BtimErrors.log,20,2007-07-31
....\.......\...........\........\files_to_build.txt,26,2007-07-31
....\.......\...........\........\hdlsynchk.tcl,107,2007-07-31
....\.......\...........\........\uart_test.dsk,996,2007-07-31
....\.......\...........\........\uart_test.hpj,890,2007-07-31
....\.......\...........\........\uart_test.v,1012,2007-07-31
....\.......\...........\........\uart_test_tbench.bk,5597,2007-07-31
....\.......\...........\........\uart_test_tbench.btim,5597,2007-07-31
....\.......\...........\........\uart_test_tbench.v,6616,2007-07-31
....\.......\...........\........\waveperl.log,37,2007-07-31
....\.......\...........\synthesis
....\.......\...........\.........\.recordref,0,2007-08-19
....\.......\...........\.........\backup
....\.......\...........\.........\rev_1
....\.......\...........\.........\.....\backup
....\.......\...........\.........\.....\coreip
....\.......\...........\.........\.....\run_options.txt,1407,2011-04-07
....\.......\...........\.........\.....\syntmp
....\.......\...........\.........\run_options.txt,1310,2007-07-30
....\.......\...........\.........\stdout.log,910,2011-04-07
....\.......\...........\.........\synthesis_identify
....\.......\...........\.........\..................\syntmp
....\.......\...........\.........\..................\......\identify.msg,0,2007-07-31
....\.......\...........\.........\..................\......\uart_test.msg,0,2007-07-31
....\.......\...........\.........\..................\......\uart_test_flink.htm,344,2007-07-31
....\.......\...........\.........\..................\uart_test.srs,11922,2007-07-31
....\.......\...........\.........\..................\uart_test.tlg,1692,2007-07-31
....\.......\...........\.........\syntmp
....\.......\...........\.........\......\sap.log,750,2007-08-19
....\.......\...........\.........\......\uart_test.msg,1955,2007-08-19
....\.......\...........\.........\......\uart_test.plg,709,2007-08-19
....\.......\...........\.........\......\uart_test_flink.htm,356,2007-08-19
....\.......\...........\.........\......\uart_test_srr.htm,41775,2007-08-19
....\.......\...........\.........\......\uart_test_toc.htm,1659,2007-08-19
....\.......\...........\.........\traplog.tlg,3925,2007-08-19
....\.......\...........\.........\uart_test.areasrr,5534,2007-08-19
....\.......\...........\.........\uart_test.edn,141685,2007-08-19
....\.......\...........\.........\uart_test.fse,0,2007-08-19
....\.......\...........\.........\uart_test.htm,340,2007-08-19
....\.......\...........\.........\uart_test.map,0,2007-08-19
....\.......\...........\.........\uart_test.sap,3062,2007-08-19
....\.......\...........\.........\uart_test.sdf,94643,2007-08-19
....\.......\...........\.........\uart_test.srd,60270,2007-08-19
....\.......\...........\.........\uart_test.srm,278918,2007-08-19
....\.......\...........\.........\uart_test.srr,37796,2007-08-19
....\.......\...........\.........\uart_test.srs,12073,2007-08-19
....\.......\...........\.........\uart_test.tlg,2464,2007-08-19
....\.......\...........\.........\uart_test_drc.rpt,6535,2007-08-19
....\.......\...........\.........\uart_test_sdc.sdc,310,2007-08-19
....\.......\...........\.........\uart_test_syn.prj,604,2011-04-07
....\.......\...........\uart.prj,5848,2011-04-07
....\.......\...........\viewdraw
....\.......\...........\........\sch
....\.......\...........\........\sym
....\.......\...........\........\vf
....\.......\...........\........\..\project.lst,59,2011-04-07
....\.......\...........\........\viewdraw.ini,1672,2011-04-07
....\.......\...........\........\wir
....\Source
....\......\Fusion_UART
....\......\...........\rec.v,2306,2007-03-19
....\......\...........\send.v,2054,2007-03-19
....\......\...........\uart_test.v,1405,2007-07-14

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