yy

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 29KB
Downloads: 4
Upload time: 2010-12-13 09:59:38
Uploader: 黄国猛
Description:   Seven voting machines when voters is greater than or equal to 4 through the green light the other hand does not pass, the yellow light. Description, just check the status of each input (through the " 1" , without " 0" ), and these states are added to determine the state values and to select the output.

File list:
yy
..\LIB.DLS,113,2010-12-06
..\seg7d.acf,15667,2010-12-06
..\seg7d.fit,2846,2010-12-06
..\seg7d.hex,34004,2010-12-06
..\seg7d.hif,3312,2010-12-06
..\seg7d.mmf,340,2010-12-06
..\seg7d.ndb,1719,2010-12-06
..\seg7d.pin,5236,2010-12-06
..\seg7d.pof,55240,2010-12-06
..\seg7d.rpt,20547,2010-12-06
..\seg7d.scf,1895,2010-12-06
..\seg7d.snf,7398,2010-12-06
..\seg7d.sof,14437,2010-12-06
..\SEG7D.sym,316,2010-12-06
..\seg7d.ttf,59691,2010-12-06
..\seg7d.vhd,459,2010-12-06
..\U0409162.DLS,1154,2010-12-06
..\U5819412.DLS,4271,2010-12-06
..\U7355204.DLS,1494,2010-12-06

Download users:

Relate files:

Comment: Add Comment

Favorite users: