Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 2KB
Downloads: 10
Upload time: 2010-11-28 10:05:40
Uploader: riversky
Description:   The module s function is to verify the implementation and the basic PC, the serial communication function. Need PC, Install a serial debugging tools to verify the functionality of the program. Program implements a receive a 10 bit (ie no parity bit) of the serial controllers, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial Porter law defined by the program parameters div_par decision can change the parameters of the corresponding Baud rate. Program the value of the current set div_par Is 0x104, the corresponding baud rate is 9600. 8 times the baud rate with a clock will be sent or received per A bit of the cycle time is divided into eight time slots in order to pass Information synchronization. The basic process is the work program, press a button SW0, the controller s serial port to the PC "Welcome", PC, after receiving the authentication data displayed is correct (serial debugging tool ASCII code set by the r

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